gateware

commit 0b9c12113b4e19ea0b9d581fe0598bebc8f00987
parent 66db679856188d4765806d6f04d7422663f3c961
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun, 26 Jan 2020 04:01:56 -0800

colorlight: ethernet experiments continue

Diffstat:
M
hdl/colorlight.lpf
 | 
13
+++++++++++++
M
hdl/colorlight.sv
 | 
92
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----
M
project/colorlight.def
 | 
1
+

3 files changed, 102 insertions(+), 4 deletions(-)
diff --git a/hdl/colorlight.lpf b/hdl/colorlight.lpf
@@ -25,6 +25,19 @@ LOCATE COMP "phy0_rxd[2]" SITE "N1";
 LOCATE COMP "phy0_rxd[3]" SITE "P1";
 LOCATE COMP "phy0_rx_dv" SITE "P2";
 
+LOCATE COMP "phy1_gtxclk" SITE "U19";
+LOCATE COMP "phy1_txd[0]" SITE "U20";
+LOCATE COMP "phy1_txd[1]" SITE "T19";
+LOCATE COMP "phy1_txd[2]" SITE "T20";
+LOCATE COMP "phy1_txd[3]" SITE "R20";
+LOCATE COMP "phy1_tx_en" SITE "P19";
+LOCATE COMP "phy1_rxc" SITE "L19";
+LOCATE COMP "phy1_rxd[0]" SITE "P20";
+LOCATE COMP "phy1_rxd[1]" SITE "N19";
+LOCATE COMP "phy1_rxd[2]" SITE "N20";
+LOCATE COMP "phy1_rxd[3]" SITE "M19";
+LOCATE COMP "phy1_rx_dv" SITE "M20";
+
 LOCATE COMP "j1r0" SITE "B3";
 LOCATE COMP "j1g0" SITE "A2";
 LOCATE COMP "j1b0" SITE "B2";
diff --git a/hdl/colorlight.sv b/hdl/colorlight.sv
@@ -3,11 +3,17 @@
 module top(
 	input wire phy_clk,
 	output wire phy_reset_n,
+
 	input wire phy0_rxc,
 	input wire [3:0]phy0_rxd,
 	input wire phy0_rx_dv,
-//	output wire glb_clk,
-//	output wire glb_bln,
+
+	output wire phy1_gtxclk,
+	output wire phy1_tx_en,
+	output wire [3:0]phy1_txd,
+
+	output wire glb_clk,
+	output wire glb_bln,
 	output wire j1r0,
 	output wire j1r1,
 	output wire j1g0,
@@ -21,18 +27,96 @@ module top(
 
 wire clk25m = phy_clk;
 
-`ifdef PLL
 wire clk125m;
 wire clk250m;
 
 pll_25_125_250 pll(
-	.clk25m_in(phy_clk_in),
+	.clk25m_in(phy_clk),
 	.clk125m_out(clk125m),
 	.clk250m_out(clk250m),
 	.locked()
 );
+
+`ifdef XXX
+reg [31:0]count1;
+always_ff @(posedge phy1_rxc) begin
+	count1 <= count1 + 32'd1;
+end
+assign glb_clk = count1[1];
+
+reg [31:0]count0;
+always_ff @(posedge phy0_rxc) begin
+	count0 <= count0 + 32'd1;
+end
+assign glb_bln = count0[1];
 `endif
 
+wire tx_clk = clk125m;
+reg tx_start = 0;
+reg tx_valid = 0;
+reg tx_error = 0;
+reg [7:0]tx_data = 8'd0;
+wire tx_ready;
+
+eth_rgmii_tx eth_tx(
+	.tx_clk(tx_clk),
+	.pin_tx_clk(phy1_gtxclk),
+	.pin_tx_en(phy1_tx_en),
+	.pin_tx_data(phy1_txd),
+	.start(tx_start),
+	.ready(tx_ready),
+	.valid(tx_valid),
+	.error(tx_error),
+	.data(tx_data)
+);
+
+
+reg [7:0]msgram[0:63];
+
+initial $readmemh("hdl/message.hex", msgram);
+
+
+reg [31:0]count1s = 32'd0;
+always_ff @(posedge tx_clk) begin
+	if (count1s == 32'd125000000) begin
+		count1s <= 32'd0;
+		tx_start <= 1;
+	end else begin
+		count1s <= count1s + 32'd1;
+		tx_start <= 0;
+	end
+end
+
+reg [7:0]xcount = 8'd0;
+reg [7:0]next_xcount;
+reg next_tx_valid;
+reg [7:0]next_tx_data;
+
+always_comb begin
+	next_xcount = xcount;
+	next_tx_valid = tx_valid;
+	next_tx_data = xcount;
+
+	if (tx_start) begin
+		next_tx_valid = 1;
+		next_xcount = 8'd0;
+	end
+
+	if (tx_valid & tx_ready) begin
+		if (xcount < 8'd64) begin
+			next_xcount = xcount + 8'd1;
+		end else begin
+			next_tx_valid = 0;
+		end
+	end
+end
+
+always_ff @(posedge tx_clk) begin
+	xcount <= next_xcount;
+	tx_valid <= next_tx_valid;
+	tx_data <= msgram[next_xcount[5:0]];
+end
+
 wire [7:0]rx_data;
 wire rx_valid;
 wire rx_sop;
diff --git a/project/colorlight.def b/project/colorlight.def
@@ -3,6 +3,7 @@ PROJECT_TYPE := nextpnr-ecp5
 PROJECT_SRCS := hdl/colorlight.sv hdl/colorlight.lpf
 PROJECT_SRCS += hdl/lattice/ecp5_pll_25_125_250.v
 PROJECT_SRCS += hdl/ethernet/eth_rgmii_rx.sv hdl/ethernet/eth_rgmii_rx_glue_ecp5.sv
+PROJECT_SRCS += hdl/ethernet/eth_rgmii_tx.sv hdl/ethernet/eth_rgmii_tx_glue_ecp5.sv
 PROJECT_SRCS += hdl/ethernet/eth_crc32_8.sv
 PROJECT_SRCS += hdl/display/display.sv hdl/display/display_timing.sv