gateware

commit 2361585429bc93c3e6e2004dfb0f1354630e3e98
parent c9583916905378daf05e700b211454b3a942757d
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun, 25 Nov 2018 14:22:52 -0800

cpu16/ice40: tweak verilog to make icecube/synplify happy

Diffstat:
M
hdl/cpu16.sv
 | 
30
+++++++++++++++++-------------
M
hdl/ice40.v
 | 
6
++++--

2 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/hdl/cpu16.sv b/hdl/cpu16.sv
@@ -164,6 +164,10 @@ always_ff @(posedge clk) begin
 		ir_ext_imm <= ir_imm_s12[11:0];
 end
 
+wire [15:0]ex_adata;
+wire [15:0]ex_bdata;
+wire [15:0]ex_alu_rdata;
+
 regs16 regs(
 	.clk(clk),
 	.asel(ir_asel),
@@ -177,11 +181,6 @@ regs16 regs(
 
 // ---- EXECUTE ----
 
-wire [15:0]ex_adata;
-wire [15:0]ex_bdata;
-
-wire [15:0]ex_alu_rdata;
-
 reg [15:0]ex_branch_tgt = 16'b0;
 reg [2:0]ex_alu_op = 3'b0;
 reg [2:0]ex_wsel = 3'b0;
@@ -283,17 +282,22 @@ module alu16(
 	output [15:0]rdata
 	);
 
+reg [15:0]r;
+
 always_comb begin
 	case (op)
-	3'b000: rdata = xdata + ydata;
-	3'b001: rdata = xdata - ydata;
-	3'b010: rdata = xdata & ydata;
-	3'b011: rdata = xdata | ydata;
-	3'b100: rdata = xdata ^ ydata;
-	3'b101: rdata = { {15 {1'b0}}, xdata < ydata };
-	3'b110: rdata = { {15 {1'b0}}, xdata >= ydata };
-	3'b111: rdata = xdata * ydata;
+	3'b000: r = xdata + ydata;
+	3'b001: r = xdata - ydata;
+	3'b010: r = xdata & ydata;
+	3'b011: r = xdata | ydata;
+	3'b100: r = xdata ^ ydata;
+	3'b101: r = { {15 {1'b0}}, xdata < ydata };
+	3'b110: r = { {15 {1'b0}}, xdata >= ydata };
+	3'b111: r = xdata * ydata;
 	endcase
 end
+
+assign rdata = r;
+
 endmodule
 
diff --git a/hdl/ice40.v b/hdl/ice40.v
@@ -114,8 +114,10 @@ end
 
 //assign out1 = cpu_reset;
 //assign out2 = cpu_raddr[0];
-assign out1 = dat_wr_req;
-assign out2 = dbg_we;
+//assign out1 = dat_wr_req;
+//assign out2 = dbg_we;
+assign out1 = clk12m;
+assign out2 = clk25m;
 
 wire cs0r = ~ins_rd_addr[8];
 wire cs1r = ins_rd_addr[8];