commit 32342c0526801658f6feeb97fb696c55ceca24cc
parent 98ef000c19752e52cd3742a280c5286478a024e5
Author: Brian Swetland <swetland@frotz.net>
Date: Tue, 28 Jan 2020 07:17:29 -0800
sdram: hw testing goop for colorlight board
- trivial write and readback test
Diffstat:
3 files changed, 142 insertions(+), 0 deletions(-)
diff --git a/hdl/colorlight-sdram.sv b/hdl/colorlight-sdram.sv
@@ -0,0 +1,98 @@
+// Copyright 2020, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`default_nettype none
+
+module top(
+ input wire phy_clk,
+
+ output sdram_clk,
+ output sdram_ras_n,
+ output sdram_cas_n,
+ output sdram_we_n,
+ output [11:0]sdram_addr,
+ inout [15:0]sdram_data,
+
+ output wire glb_clk,
+ output wire glb_bln,
+ output wire j1r0,
+ output wire j1r1,
+ output wire j1g0,
+ output wire j1g1,
+ output wire j1b0,
+ output wire j1b1,
+ output wire glb_a,
+ output wire glb_b,
+ input wire btn
+);
+
+wire clk25m = phy_clk;
+
+wire clk125m;
+wire clk250m;
+
+pll_25_125_250 pll(
+ .clk25m_in(phy_clk),
+ .clk125m_out(clk125m),
+ .clk250m_out(clk250m),
+ .locked()
+);
+
+wire [15:0]info;
+wire info_e;
+
+testbench #(
+ .T_PWR_UP(25000),
+ .T_RI(1900)
+ ) test0 (
+ .clk(clk125m),
+ .error(),
+ .done(),
+ .sdram_clk(sdram_clk),
+ .sdram_ras_n(sdram_ras_n),
+ .sdram_cas_n(sdram_cas_n),
+ .sdram_we_n(sdram_we_n),
+ .sdram_addr(sdram_addr),
+`ifdef verilator
+ .sdram_data_i(sdram_data),
+ .sdram_data_o(),
+`else
+ .sdram_data(sdram_data),
+`endif
+ .info(info),
+ .info_e(info_e)
+);
+
+
+assign j1r1 = j1r0;
+assign j1b1 = j1b0;
+assign j1g1 = j1g0;
+
+reg [11:0]waddr = 12'd0;
+
+always_ff @(posedge clk125m ) begin
+ waddr <= (info_e) ? (waddr + 12'd2) : waddr;
+end
+
+display #(
+ .BPP(1),
+ .RGB(1),
+ .WIDE(0),
+ .HEXMODE(1)
+ ) display0 (
+ .clk(clk25m),
+ .red(j1r0),
+ .grn(j1g0),
+ .blu(j1b0),
+ .hsync(glb_a),
+ .vsync(glb_b),
+ .active(),
+ .frame(),
+ .wclk(clk125m),
+ .waddr(waddr),
+ .wdata(info),
+ .we(info_e)
+);
+
+endmodule
+
diff --git a/hdl/colorlight.lpf b/hdl/colorlight.lpf
@@ -53,3 +53,38 @@ LOCATE COMP "glb_clk" SITE "C18";
LOCATE COMP "glb_alat" SITE "J18";
LOCATE COMP "glb_bln" SITE "H16";
+LOCATE COMP "sdram_data[0]" SITE "D15";
+LOCATE COMP "sdram_data[1]" SITE "E14";
+LOCATE COMP "sdram_data[2]" SITE "E13";
+LOCATE COMP "sdram_data[3]" SITE "D12";
+LOCATE COMP "sdram_data[4]" SITE "E12";
+LOCATE COMP "sdram_data[5]" SITE "D11";
+LOCATE COMP "sdram_data[6]" SITE "C10";
+LOCATE COMP "sdram_data[7]" SITE "B17";
+LOCATE COMP "sdram_data[8]" SITE "B8";
+LOCATE COMP "sdram_data[9]" SITE "A8";
+LOCATE COMP "sdram_data[10]" SITE "C7";
+LOCATE COMP "sdram_data[11]" SITE "A7";
+LOCATE COMP "sdram_data[12]" SITE "A6";
+LOCATE COMP "sdram_data[13]" SITE "B6";
+LOCATE COMP "sdram_data[14]" SITE "A5";
+LOCATE COMP "sdram_data[15]" SITE "B5";
+
+LOCATE COMP "sdram_addr[0]" SITE "B13";
+LOCATE COMP "sdram_addr[1]" SITE "C14";
+LOCATE COMP "sdram_addr[2]" SITE "A16";
+LOCATE COMP "sdram_addr[3]" SITE "A17";
+LOCATE COMP "sdram_addr[4]" SITE "B16";
+LOCATE COMP "sdram_addr[5]" SITE "B15";
+LOCATE COMP "sdram_addr[6]" SITE "A14";
+LOCATE COMP "sdram_addr[7]" SITE "A13";
+LOCATE COMP "sdram_addr[8]" SITE "A12";
+LOCATE COMP "sdram_addr[9]" SITE "A11";
+LOCATE COMP "sdram_addr[10]" SITE "B12";
+LOCATE COMP "sdram_addr[11]" SITE "B11";
+
+LOCATE COMP "sdram_we_n" SITE "A10";
+LOCATE COMP "sdram_cas_n" SITE "A9";
+LOCATE COMP "sdram_ras_n" SITE "B10";
+LOCATE COMP "sdram_clk" SITE "B9";
+
diff --git a/project/colorlight-sdram.def b/project/colorlight-sdram.def
@@ -0,0 +1,9 @@
+PROJECT_TYPE := nextpnr-ecp5
+
+PROJECT_SRCS := hdl/colorlight-sdram.sv hdl/colorlight.lpf
+PROJECT_SRCS += hdl/lattice/ecp5_pll_25_125_250.v
+PROJECT_SRCS += hdl/display/display.sv hdl/display/display_timing.sv
+PROJECT_SRCS += hdl/sdram/testbench.sv
+PROJECT_SRCS += hdl/sdram/sdram.sv hdl/sdram/sdram_glue_ecp5.sv
+
+PROJECT_NEXTPNR_OPTS := --25k --package CABGA381 --speed 6
