gateware

commit 38ba90f150915b99d24ec4216254ef503f01bfa1
parent 7a8aca3c23f510c68aff1a6d2beb9fe41e12aa26
Author: Brian Swetland <swetland@frotz.net>
Date:   Sat, 17 Nov 2018 11:42:27 -0800

vga: provide dedicated videoram write clock

The CPU and debug interface don't necessarily use the
VGA clock.  This allows them to more safely interact
with the video ram from their clock domain.

Diffstat:
M
hdl/ice40.v
 | 
3
++-
M
hdl/vga/vga40x30x2.v
 | 
5
++++-
M
hdl/vga/videoram.v
 | 
11
++++++++---

3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/hdl/ice40.v b/hdl/ice40.v
@@ -128,7 +128,8 @@ vga40x30x2 vga(
 	.vs(vga_vsync),
 	.vram_waddr(waddr[10:0]),
 	.vram_wdata(wdata[7:0]),
-	.vram_we(we & cs_vram)
+	.vram_we(we & cs_vram),
+	.vram_clk(sys_clk)
 	);
 
 endmodule
diff --git a/hdl/vga/vga40x30x2.v b/hdl/vga/vga40x30x2.v
@@ -6,6 +6,7 @@ module vga40x30x2(
 	output [1:0]blu,
 	output hs,
 	output vs,
+	input vram_clk,
 	input [10:0]vram_waddr,
 	input [7:0]vram_wdata,
 	input vram_we
@@ -51,9 +52,11 @@ pixeldata pixeldata0(
 	);
 
 videoram #(8,11) vram(
-        .clk(clk25m),
+        .rclk(clk25m),
+	.re(1'b1),
         .rdata(vram_rdata),
         .raddr(vram_raddr),
+	.wclk(vram_clk),
         .we(vram_we),
         .wdata(vram_wdata[7:0]),
         .waddr(vram_waddr[10:0])
diff --git a/hdl/vga/videoram.v b/hdl/vga/videoram.v
@@ -5,9 +5,10 @@
 `timescale 1ns/1ns
 
 module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) (
-	input clk, input we,
+	input wclk, input we,
 	input [AWIDTH-1:0] waddr,
 	input [DWIDTH-1:0] wdata,
+	input rclk, input re,
 	input [AWIDTH-1:0] raddr,
 	output reg [DWIDTH-1:0] rdata
 	);
@@ -16,10 +17,14 @@ reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
 
 initial $readmemh("vram.txt", mem);
 
-always @(posedge clk) begin
+always @(posedge wclk) begin
 	if (we)
 		mem[waddr] <= wdata;
-	rdata <= mem[raddr];
+end
+
+always @(posedge rclk) begin
+	if (re)
+		rdata <= mem[raddr];
 end
 
 endmodule