commit 7a8aca3c23f510c68aff1a6d2beb9fe41e12aa26
parent 1ddac262ea0a789d650a292652067070417a105f
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 17 Nov 2018 11:35:36 -0800
support building for ice40up5k dev board w/ icestorm
- Makefile changes for yosys + arachne-pnr + icepack
- use the PLL with pass-through to keep the 12M clock
as well as generate the 25M vga clock
- updated constraints file
- some tidying
Diffstat:
5 files changed, 97 insertions(+), 57 deletions(-)
diff --git a/Makefile b/Makefile
@@ -1,19 +1,43 @@
-SRCS := hdl/testbench.sv
-SRCS += hdl/simram.sv
-SRCS += hdl/cpu/cpu.v hdl/cpu/alu.v hdl/cpu/regfile.v
+CPU_SRCS := hdl/cpu/cpu.v hdl/cpu/alu.v hdl/cpu/regfile.v
-VERILATOR := /work/verilator/bin/verilator
+VGA_SRCS := hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
+
+VSIM_SRCS := hdl/testbench.sv hdl/simram.sv $(CPU_SRCS)
+
+ICE40_SRCS := hdl/ice40.v hdl/spi_debug_ifc.v hdl/lattice/pll_12_25.v
+ICE40_SRCS += $(CPU_SRCS) $(VGA_SRCS)
+
+VERILATOR := verilator
+ARACHNEPNR := arachne-pnr
+YOSYS := yosys
+ICEPACK := icepack
VOPTS := --top-module testbench --Mdir out --exe ../src/testbench.cpp --cc -CFLAGS -DTRACE --trace
-all: out/Vtestbench out/a16 out/d16 out/icetool
+all: out/Vtestbench out/ice40.bin out/a16 out/d16 out/icetool
-out/Vtestbench: $(SRCS) src/testbench.cpp
+out/Vtestbench: $(VSIM_SRCS) src/testbench.cpp
@mkdir -p out
- @$(VERILATOR) $(VOPTS) $(SRCS)
+ @$(VERILATOR) $(VOPTS) $(VSIM_SRCS)
@make -C out -f Vtestbench.mk
+out/ice40.bin: out/ice40.asc
+ @mkdir -p out
+ $(ICEPACK) $< $@
+
+out/ice40.lint: $(ICE40_SRCS)
+ @mkdir -p out
+ $(VERILATOR) --top-module top --lint-only $(ICE40_SRCS)
+
+out/ice40.blif: $(ICE40_SRCS) out/ice40.lint
+ @mkdir -p out
+ $(YOSYS) -p 'synth_ice40 -top top -blif out/ice40.blif' $(ICE40_SRCS) 2>&1 | tee out/ice40.synth.log
+
+out/ice40.asc: out/ice40.blif
+ @mkdir -p out
+ $(ARACHNEPNR) -d 5k -p sg48 -o out/ice40.asc -p hdl/ice40up.pcf out/ice40.blif 2>&1 | tee out/ice40.pnr.log
+
run: out/Vtestbench out/test.hex
./out/Vtestbench -trace out/trace.vcd -dump out/memory.bin -load out/test.hex
diff --git a/hdl/ice40.sdc b/hdl/ice40.sdc
@@ -1,5 +1,5 @@
-create_clock -period 83.333 -name {clk12m} [get_ports {clk12m}]
+create_clock -period 83.333 -name {clk12m_in} [get_ports {clk12m_in}]
create_clock -period 166.666 -name {spi_clk} [get_ports {spi_clk}]
diff --git a/hdl/ice40.v b/hdl/ice40.v
@@ -4,7 +4,7 @@
`timescale 1ns / 1ps
module top(
- input clk12m,
+ input clk12m_in,
output [1:0]vga_r,
output [1:0]vga_g,
output [1:0]vga_b,
@@ -18,8 +18,17 @@ module top(
output out2
);
+wire clk12m;
wire clk25m;
+pll_12_25 pll0(
+ .clk12m_in(clk12m_in),
+ .clk12m_out(clk12m),
+ .clk25m_out(clk25m),
+ .lock(),
+ .reset(1'b1)
+ );
+
wire sys_clk = clk12m;
wire [15:0]cpu_waddr /* synthesis syn_keep=1 */;
@@ -110,14 +119,6 @@ sram ram1(
.we(we & cs1w & cs_sram)
);
-pll_12_25 pll0(
- .REFERENCECLK(clk12m),
- .PLLOUTGLOBAL(clk25m),
- .PLLOUTCORE(),
- .LOCK(),
- .RESET(1'b1)
- );
-
vga40x30x2 vga(
.clk25m(clk25m),
.red(vga_r),
@@ -142,7 +143,7 @@ module sram(
input we
);
-`ifdef verilator
+`ifndef uselatticeprim
reg [15:0]mem[255:0];
reg [15:0]ra;
always @(posedge clk) begin
@@ -150,8 +151,8 @@ always @(posedge clk) begin
mem[waddr[7:0]] <= wdata;
if (re)
ra <= raddr;
- rdata = mem[ra[7:0]];
end
+assign rdata = mem[ra[7:0]];
`else
SB_RAM256x16 sram_inst(
.RDATA(rdata),
diff --git a/hdl/ice40up.pcf b/hdl/ice40up.pcf
@@ -0,0 +1,18 @@
+set_io clk12m_in 35
+
+set_io vga_r[0] 23
+set_io vga_g[0] 25
+set_io vga_r[1] 26
+set_io vga_g[1] 27
+set_io vga_b[1] 32
+set_io vga_b[0] 31
+set_io vga_hsync 34
+set_io vga_vsync 43
+
+set_io spi_miso 14
+set_io spi_mosi 17
+set_io spi_clk 15
+set_io spi_cs 16
+
+set_io out1 3
+set_io out2 4
diff --git a/hdl/lattice/pll_12_25.v b/hdl/lattice/pll_12_25.v
@@ -1,45 +1,42 @@
-module pll_12_25(REFERENCECLK,
- PLLOUTCORE,
- PLLOUTGLOBAL,
- RESET,
- LOCK);
+module pll_12_25(
+ input clk12m_in,
+ output clk12m_out,
+ output clk25m_out,
+ input reset,
+ output lock
+ );
-input REFERENCECLK;
-input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
-output PLLOUTCORE;
-output PLLOUTGLOBAL;
-output LOCK;
+`ifndef verilator
-`ifdef verilator
-assign PLLOUTCORE = REFERENCECLK;
-assign PLLOUTGLOBAL = REFERENCECLK;
-`else
-SB_PLL40_CORE pll_12_25_inst(.REFERENCECLK(REFERENCECLK),
- .PLLOUTCORE(PLLOUTCORE),
- .PLLOUTGLOBAL(PLLOUTGLOBAL),
- .EXTFEEDBACK(),
- .DYNAMICDELAY(),
- .RESETB(RESET),
- .BYPASS(1'b0),
- .LATCHINPUTVALUE(),
- .LOCK(LOCK),
- .SDI(),
- .SDO(),
- .SCLK());
+// generated by icecube2 wizard
+SB_PLL40_2_PAD pll_inst(.PACKAGEPIN(clk12m_in),
+ .PLLOUTCOREA(),
+ .PLLOUTCOREB(),
+ .PLLOUTGLOBALA(clk12m_out),
+ .PLLOUTGLOBALB(clk25m_out),
+ .EXTFEEDBACK(),
+ .DYNAMICDELAY(),
+ .RESETB(reset),
+ .BYPASS(1'b0),
+ .LATCHINPUTVALUE(),
+ .LOCK(lock),
+ .SDI(),
+ .SDO(),
+ .SCLK());
//\\ Fin=12, Fout=25;
-defparam pll_12_25_inst.DIVR = 4'b0001;
-defparam pll_12_25_inst.DIVF = 7'b1000010;
-defparam pll_12_25_inst.DIVQ = 3'b100;
-defparam pll_12_25_inst.FILTER_RANGE = 3'b001;
-defparam pll_12_25_inst.FEEDBACK_PATH = "SIMPLE";
-defparam pll_12_25_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
-defparam pll_12_25_inst.FDA_FEEDBACK = 4'b0000;
-defparam pll_12_25_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
-defparam pll_12_25_inst.FDA_RELATIVE = 4'b0000;
-defparam pll_12_25_inst.SHIFTREG_DIV_MODE = 2'b00;
-defparam pll_12_25_inst.PLLOUT_SELECT = "GENCLK";
-defparam pll_12_25_inst.ENABLE_ICEGATE = 1'b0;
+defparam pll_inst.DIVR = 4'b0000;
+defparam pll_inst.DIVF = 7'b1000010;
+defparam pll_inst.DIVQ = 3'b101;
+defparam pll_inst.FILTER_RANGE = 3'b001;
+defparam pll_inst.FEEDBACK_PATH = "SIMPLE";
+defparam pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
+defparam pll_inst.FDA_FEEDBACK = 4'b0000;
+defparam pll_inst.SHIFTREG_DIV_MODE = 2'b00;
+defparam pll_inst.PLLOUT_SELECT_PORTB = "GENCLK";
+defparam pll_inst.ENABLE_ICEGATE_PORTA = 1'b0;
+defparam pll_inst.ENABLE_ICEGATE_PORTB = 1'b0;
+
`endif
endmodule
