commit 5a19e93f85d56653aa5c62c9ce906795e4c0abbb
parent b8e750af8434a0880e8b64c878b75586213c45ee
Author: Brian Swetland <swetland@frotz.net>
Date: Thu, 6 Feb 2020 15:09:55 -0800
ulx3s-sdram: setup hdmi display output
Diffstat:
3 files changed, 100 insertions(+), 17 deletions(-)
diff --git a/hdl/ulx3s-sdram.sv b/hdl/ulx3s-sdram.sv
@@ -3,9 +3,12 @@
`default_nettype none
+`define HAS_SDRAM
+
module top(
input wire clk_25mhz,
+`ifdef HAS_SDRAM
output wire [7:0]led,
output sdram_clk,
@@ -17,24 +20,100 @@ module top(
output sdram_cke,
output sdram_cs_n,
- output [1:0]sdram_dqm
+ output [1:0]sdram_dqm,
+`endif
+
+ output [3:0]gpdi_dn,
+ output [3:0]gpdi_dp // C R G B
);
+`ifdef HAS_SDRAM
assign sdram_cke = 1;
assign sdram_cs_n = 0;
assign sdram_dqm = 2'b00;
+`endif
wire clk25m = clk_25mhz;
-wire clk100m;
+`ifdef SLOWCLOCK
+wire clk100m;
pll_25_100 pll(
.clk25m_in(clk25m),
.clk100m_out(clk100m),
.locked()
);
-
wire testclk = clk100m;
+`else
+wire clk125m;
+wire clk250m;
+pll_25_125_250 pll(
+ .clk25m_in(clk25m),
+ .clk125m_out(clk125m),
+ .clk250m_out(clk250m),
+ .locked()
+);
+wire testclk = clk125m;
+`endif
+wire r,g,b;
+
+wire [7:0]red = {8{r}};
+wire [7:0]grn = {8{g}};
+wire [7:0]blu = {8{b}};
+
+wire active;
+wire hsync;
+wire vsync;
+
+dvi_backend dvi0 (
+ .pixclk(clk25m),
+ .pixclk5x(clk125m),
+ .pin_dvi_dp(gpdi_dp),
+ .pin_dvi_dn(gpdi_dn),
+ .hsync(hsync),
+ .vsync(vsync),
+ .active(active),
+ .red(red),
+ .grn(grn),
+ .blu(blu)
+);
+
+wire [15:0]info;
+wire info_e;
+
+reg [10:0]waddr = 11'd0;
+wire [10:0]waddr_next = (waddr == 11'd1199) ? 11'd0 : (waddr + 11'd1);
+always_ff @(posedge testclk) begin
+ waddr <= (info_e) ? waddr_next : waddr;
+end
+
+display #(
+ .BPP(1),
+ .RGB(1),
+ .WIDE(0),
+ .HEXMODE(1)
+ ) display0 (
+ .clk(clk25m),
+ .red(r),
+ .grn(g),
+ .blu(b),
+ .hsync(hsync),
+ .vsync(vsync),
+ .active(active),
+ .frame(),
+ .wclk(testclk),
+`ifdef HAS_SDRAM
+ .waddr({waddr,1'b0}),
+ .wdata(info),
+ .we(info_e)
+`else
+ .waddr(0),
+ .wdata(16'h0),
+ .we(0)
+`endif
+);
+
+`ifdef HAS_SDRAM
wire [24:0]rd_addr;
wire [15:0]rd_data;
wire [3:0]rd_len;
@@ -72,8 +151,8 @@ testbench #(
.wr_req(wr_req),
.wr_ack(wr_ack),
- .info(),
- .info_e()
+ .info(info),
+ .info_e(info_e)
);
sdram #(
@@ -83,8 +162,8 @@ sdram #(
.T_PWR_UP(25000),
.T_RI(750),
.T_RCD(3),
- .CLK_SHIFT(0),
- .CLK_DELAY(127)
+ .CLK_SHIFT(1),
+ .CLK_DELAY(0)
) sdram0 (
.clk(testclk),
.reset(0),
@@ -115,6 +194,7 @@ sdram #(
.wr_req(wr_req),
.wr_ack(wr_ack)
);
+`endif
endmodule
diff --git a/hdl/ulx3s.lpf b/hdl/ulx3s.lpf
@@ -309,16 +309,16 @@ LOCATE COMP "gpdi_ethn" SITE "B20"; # Ethernet -
LOCATE COMP "gpdi_cec" SITE "A18";
LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC
LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12
-IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4;
-IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4;
-IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4;
-IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4;
-IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4;
-IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4;
-IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4;
-IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4;
-IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33D DRIVE=4;
-IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33D DRIVE=4;
+IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpdi_ethp" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpdi_ethn" IO_TYPE=LVCMOS33;
IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
diff --git a/project/ulx3s-sdram.def b/project/ulx3s-sdram.def
@@ -2,8 +2,11 @@ PROJECT_TYPE := nextpnr-ecp5
PROJECT_SRCS := hdl/ulx3s-sdram.sv hdl/ulx3s.lpf
PROJECT_SRCS += hdl/lattice/ecp5_pll_25_100.v
+PROJECT_SRCS += hdl/lattice/ecp5_pll_25_125_250.v
PROJECT_SRCS += hdl/sdram/memtest1.sv
PROJECT_SRCS += hdl/sdram/sdram.sv hdl/sdram/sdram_glue_ecp5.sv
PROJECT_SRCS += hdl/xorshift.sv
+PROJECT_SRCS += hdl/display/display.sv hdl/display/display_timing.sv
+PROJECT_SRCS += hdl/display/dvi-encoder.sv hdl/display/dvi-backend.sv
PROJECT_NEXTPNR_OPTS := --85k --package CABGA381 --speed 6
