gateware

commit 6ef5a58eb0c8908a70335e429ebca27207e4e5d7
parent 1415fc3e734338cb5322ee300721be6660b63377
Author: Brian Swetland <swetland@frotz.net>
Date:   Wed, 22 Jan 2020 18:22:36 -0800

display: check in simulator test

Diffstat:
A
hdl/display/testbench.sv
 | 
37
+++++++++++++++++++++++++++++++++++++
M
project/display.def
 | 
3
++-

2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/hdl/display/testbench.sv b/hdl/display/testbench.sv
@@ -0,0 +1,37 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`default_nettype none
+
+`timescale 1ns / 1ps
+
+`define HEX_PATHS
+
+module testbench(
+        input clk,
+	output [3:0]vga_red,
+	output [3:0]vga_grn,
+	output [3:0]vga_blu,
+	output vga_hsync,
+	output vga_vsync,
+	output vga_frame
+        );
+
+display #(
+	.BPP(4),
+	)vga(
+	.clk(clk),
+	.red(vga_red),
+	.grn(vga_grn),
+	.blu(vga_blu),
+	.hsync(vga_hsync),
+	.vsync(vga_vsync),
+	.frame(vga_frame),
+	.active(),
+	.waddr(12'b0),
+	.wdata(16'b0),
+	.we(1'b0),
+	.wclk(clk)
+	);
+
+endmodule
diff --git a/project/display.def b/project/display.def
@@ -1,6 +1,7 @@
 
 PROJECT_TYPE := verilator-sim
 
-PROJECT_SRCS := hdl/testdisplay.sv hdl/display/display.sv hdl/display/display_timing.sv
+PROJECT_SRCS := hdl/display/testbench.sv
+PROJECT_SRCS += hdl/display/display.sv hdl/display/display_timing.sv
 
 PROJECT_VOPTS := -CFLAGS -DVGA