commit a7f51b26a91827349c95fded8d890c155e617737 parent 857151be43832f3ffdf43e59670e47a6bdc11f1b Author: Brian Swetland <swetland@frotz.net> Date: Sun, 26 Jan 2020 15:46:41 -0800 build: deposit simulation logs and traces in out/sim/... - traces as out/sim/{project}.vcd - logfiles as out/sim/{project}.log Diffstat:
| M | build/verilator-sim.mk | | | 6 | ++++-- |
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/build/verilator-sim.mk b/build/verilator-sim.mk @@ -33,9 +33,11 @@ $(PROJECT_BIN): $(PROJECT_SRCS) $(PROJECT_DEF) src/testbench.cpp $(PROJECT_NAME): $(PROJECT_BIN) -$(PROJECT_RUN): _LOGFILE := $(PROJECT_OBJDIR)/simulation.log +$(PROJECT_RUN): _LOGFILE := out/sim/$(PROJECT_NAME).log +$(PROJECT_RUN): _VCDFILE := out/sim/$(PROJECT_NAME).vcd $(PROJECT_RUN): $(PROJECT_BIN) - @$< > $(_LOGFILE) + @mkdir -p out/sim + @$< -trace $(_VCDFILE) > $(_LOGFILE) ALL_TARGETS += $(PROJECT_NAME) $(PROJECT_RUN) ALL_BUILDS += $(PROJECT_NAME)