gateware

commit accf776895d300e20209e16c3e5c72c4b3aa66c6
parent 18a6ba36ae4b9aa6938e29a98e4b94398b88f516
Author: Brian Swetland <swetland@frotz.net>
Date:   Tue,  4 Feb 2020 16:55:54 -0800

build: pass verilog defines vi PROJECT_VERILOG_DEFS

Diffstat:
M
build/init.mk
 | 
1
+
M
build/nextpnr-ecp5.mk
 | 
2
++

2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/build/init.mk b/build/init.mk
@@ -27,6 +27,7 @@ $(eval PROJECT_TYPE :=)\
 $(eval PROJECT_PART :=)\
 $(eval PROJECT_SRCS :=)\
 $(eval PROJECT_VOPTS :=)\
+$(eval PROJECT_VERILOG_DEFS :=)\
 $(eval PROJECT_NEXTPNR_OPTS :=)\
 $(eval include $(PROJECT_DEF))\
 $(eval PROJECT_NAME := $(patsubst project/%.def,%,$(PROJECT_DEF)))\
diff --git a/build/nextpnr-ecp5.mk b/build/nextpnr-ecp5.mk
@@ -17,10 +17,12 @@ PROJECT_LPF_SRCS := $(filter %.lpf,$(PROJECT_SRCS))
 
 $(PROJECT_YS): _SRCS := $(PROJECT_VLG_SRCS)
 $(PROJECT_YS): _JSON := $(PROJECT_JSON)
+$(PROJECT_YS): _DEFS := $(PROJECT_VERILOG_DEFS)
 $(PROJECT_YS): $(PROJECT_SRCS) $(PROJECT_DEF) build/nextpnr-ecp5.mk
 	@mkdir -p $(dir $@)
 	@echo GENERATING: $@
 	@echo verilog_defines -DHEX_PATHS -DYOSYS > $@
+	@for def in $(_DEFS); do echo verilog_defines -D$$def; done >> $@
 	@for src in $(_SRCS); do echo read_verilog -sv $$src; done >> $@
 	@echo synth_ecp5 -top top -json $(_JSON) >> $@