gateware

commit afafdc48bb6a38316e626feb7b0997202cc9c691
parent 2361585429bc93c3e6e2004dfb0f1354630e3e98
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun, 25 Nov 2018 14:56:22 -0800

ice40 tweaks

- make character ram sync (so it'll infer brams)
- map clk12m/clk25m to test points

Diffstat:
M
hdl/ice40.v
 | 
5
+++--
M
hdl/vga/chardata.v
 | 
7
+++++++

2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hdl/ice40.v b/hdl/ice40.v
@@ -21,6 +21,9 @@ module top(
 wire clk12m;
 wire clk25m;
 
+assign out1 = clk12m;
+assign out2 = clk25m;
+
 pll_12_25 pll0(
 	.clk12m_in(clk12m_in),
 	.clk12m_out(clk12m),
@@ -116,8 +119,6 @@ end
 //assign out2 = cpu_raddr[0];
 //assign out1 = dat_wr_req;
 //assign out2 = dbg_we;
-assign out1 = clk12m;
-assign out2 = clk25m;
 
 wire cs0r = ~ins_rd_addr[8];
 wire cs1r = ins_rd_addr[8];
diff --git a/hdl/vga/chardata.v b/hdl/vga/chardata.v
@@ -48,7 +48,14 @@ assign vram_addr = { line[7:3], next_xpos };
 // the display line to further index into the correct pattern
 wire [9:0] pattern_addr = { vram_data[6:0], line[2:0] };
 
+`ifdef ASYNC_ROM
 wire [7:0] cdata = pattern_rom[pattern_addr];
+`else
+reg [7:0] cdata;
+always_ff @(posedge clk)
+	cdata <= pattern_rom[pattern_addr];
+`endif
+
 
 // the high bit of the pattern shift register is used to
 // select the FG or BG color and feed out to the vga core