gateware

commit b1ffb705c7ab63c9f1edbe9e11c1535beab5301c
parent 2e83889010b572ccf962b927fe82f3ac23773bb7
Author: Brian Swetland <swetland@frotz.net>
Date:   Tue,  4 Feb 2020 03:16:38 -0800

colorlight-sdram: use 100MHz clock for now

Diffstat:
M
hdl/colorlight-sdram.sv
 | 
18
+++++++++++++++---
M
hdl/colorlight.lpf
 | 
1
+
M
project/colorlight-sdram.def
 | 
1
+

3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/hdl/colorlight-sdram.sv b/hdl/colorlight-sdram.sv
@@ -28,6 +28,7 @@ module top(
 
 wire clk25m = phy_clk;
 
+`ifdef CLK125
 wire clk125m;
 wire clk250m;
 
@@ -37,6 +38,17 @@ pll_25_125_250 pll(
 	.clk250m_out(clk250m),
 	.locked()
 );
+`else
+wire clk100m;
+
+pll_25_100 pll(
+	.clk25m_in(phy_clk),
+	.clk100m_out(clk100m),
+	.locked()
+);
+`endif
+
+wire testclk = clk100m;
 
 wire [15:0]info;
 wire info_e;
@@ -45,7 +57,7 @@ testbench #(
 	.T_PWR_UP(25000), 
 	.T_RI(1900)
 	) test0 (
-	.clk(clk125m),
+	.clk(testclk),
 	.error(),
 	.done(),
 	.sdram_clk(sdram_clk),
@@ -70,7 +82,7 @@ assign j1g1 = j1g0;
 
 reg [11:0]waddr = 12'd0;
 
-always_ff @(posedge clk125m ) begin
+always_ff @(posedge testclk) begin
 	waddr <= (info_e)  ? (waddr + 12'd2) : waddr;
 end
 
@@ -88,7 +100,7 @@ display #(
         .vsync(glb_b),
         .active(),
         .frame(),
-        .wclk(clk125m),
+        .wclk(testclk),
         .waddr(waddr),
         .wdata(info),
         .we(info_e)
diff --git a/hdl/colorlight.lpf b/hdl/colorlight.lpf
@@ -3,6 +3,7 @@ FREQUENCY NET "phy0_rxc" 125 MHZ;
 
 fREQUENCY NET "clk250m" 250 MHZ;
 FREQUENCY NET "clk125m" 125 MHZ;
+FREQUENCY NET "clk100m" 100 MHZ;
 
 LOCATE COMP "phy_clk" SITE "P3";
 LOCATE COMP "phy_reset_n" SITE "P4";
diff --git a/project/colorlight-sdram.def b/project/colorlight-sdram.def
@@ -2,6 +2,7 @@ PROJECT_TYPE := nextpnr-ecp5
 
 PROJECT_SRCS := hdl/colorlight-sdram.sv hdl/colorlight.lpf
 PROJECT_SRCS += hdl/lattice/ecp5_pll_25_125_250.v
+PROJECT_SRCS += hdl/lattice/ecp5_pll_25_100.v
 PROJECT_SRCS += hdl/display/display.sv hdl/display/display_timing.sv
 PROJECT_SRCS += hdl/sdram/testbench.sv hdl/sdram/test.hex
 PROJECT_SRCS += hdl/sdram/sdram.sv hdl/sdram/sdram_glue_ecp5.sv