gateware

commit c74f68f48a3f170b187ebc71ee48fdc3175c63c0
parent 64639a7d709b6d705bb20a247935b1d320b04bdd
Author: Brian Swetland <swetland@frotz.net>
Date:   Fri, 24 Jan 2020 17:58:55 -0800

testbench: minor cleanup

- rebuilt verilator sim targets if testbench.cpp changes
- fix first clk period being too long

Diffstat:
M
build/verilator-sim.mk
 | 
2
+-
M
src/testbench.cpp
 | 
23
+++++++++--------------

2 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/build/verilator-sim.mk b/build/verilator-sim.mk
@@ -24,7 +24,7 @@ $(PROJECT_BIN): _SRCS := $(PROJECT_VLG_SRCS)
 $(PROJECT_BIN): _OPTS := $(PROJECT_OPTS)
 $(PROJECT_BIN): _DIR := $(PROJECT_OBJDIR)
 
-$(PROJECT_BIN): $(PROJECT_SRCS) $(PROJECT_DEF)
+$(PROJECT_BIN): $(PROJECT_SRCS) $(PROJECT_DEF) src/testbench.cpp
 	@mkdir -p $(_DIR) bin
 	@echo "COMPILE (verilator): $(_NAME)"
 	@$(VERILATOR) $(_OPTS) $(_SRCS)
diff --git a/src/testbench.cpp b/src/testbench.cpp
@@ -200,28 +200,25 @@ int main(int argc, char **argv) {
 
 	Vtestbench *testbench = new Vtestbench;
 	testbench->clk = 0;
+// first tick, line up with gtk's vert lines
+	testbench->eval();
 
 #ifdef TRACE
 	Verilated::traceEverOn(true);
 	VerilatedVcdC* tfp = new VerilatedVcdC;
 	testbench->trace(tfp, 99);
 	tfp->open(vcdname);
-#endif
-
-// first tick, line up with gtk's vert lines
-	testbench->eval();
-#ifdef TRACE
 	tfp->dump(now);
-	now += 10;
+#define SAVETRACE() tfp->dump(now)
+#else
+#define SAVETRACE() do {} while (0)
 #endif
 
 	while (!Verilated::gotFinish()) {
+		now += 5;
 		testbench->clk = 1;
 		testbench->eval();
-#ifdef TRACE
-		tfp->dump(now);
-		now += 5;
-#endif
+		SAVETRACE();
 #ifdef VGA
 		if (vga_tick(testbench->vga_hsync, testbench->vga_vsync,
 			     testbench->vga_frame, testbench->vga_red,
@@ -229,12 +226,10 @@ int main(int argc, char **argv) {
 			break;
 		}
 #endif
+		now += 5;
 		testbench->clk = 0;
 		testbench->eval();
-#ifdef TRACE
-		tfp->dump(now);
-		now += 5;
-#endif
+		SAVETRACE();
 	}
 #ifdef TRACE
 	tfp->close();