commit d84b7d8a5ed417a9f67f2d6c502b575d0ecc1588
parent 555b78efa9093a04f1fd261af60f244bda1d2249
Author: Brian Swetland <swetland@frotz.net>
Date: Sun, 18 Nov 2018 17:49:02 -0800
tidying up a bit
- tell yosys to tolerate some systemverilog constructs
- use some sv in cpu.v
- rename tests with dashes instead of underscores
(what was I thinking?!)
- add a few more tests
- make tests now sorts them so they run in the expected order
Diffstat:
7 files changed, 69 insertions(+), 10 deletions(-)
diff --git a/Makefile b/Makefile
@@ -31,11 +31,11 @@ out/ice40.lint: $(ICE40_SRCS)
$(VERILATOR) --top-module top --lint-only $(ICE40_SRCS)
@touch out/ice40.lint
-out/ice40.ys: $(ICE40_SRCS)
+out/ice40.ys: $(ICE40_SRCS) Makefile
@mkdir -p out
@echo generating $@
@echo verilog_defines -DHEX_PATHS > $@
- @for src in $(ICE40_SRCS) ; do echo read_verilog $$src ; done >> $@
+ @for src in $(ICE40_SRCS) ; do echo read_verilog -sv $$src ; done >> $@
@echo synth_ice40 -top top -blif out/ice40.blif >> $@
out/ice40.blif: out/ice40.ys out/ice40.lint
@@ -69,7 +69,7 @@ out/icetool: src/icetool.c src/ftdi.c src/ftdi.h
TEST_DEPS := out/Vtestbench out/a16 out/d16 tests/runtest
-TESTS := $(wildcard tests/*.s)
+TESTS := $(sort $(wildcard tests/*.s))
RESULTS := $(patsubst %.s,out/%.s.status,$(TESTS))
diff --git a/hdl/cpu/cpu.v b/hdl/cpu/cpu.v
@@ -102,7 +102,7 @@ wire [AWIDTH-1:0]pc_next = exe_branch ? branch_target : (pc + 16'd1);
reg do_load_pc;
-always @(*) begin
+always_comb begin
ir_next = ir;
ir_valid_next = ir_valid;
ir_loading_next = ir_loading;
@@ -139,7 +139,7 @@ always @(*) begin
end
end
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
if (reset) begin
pc <= 16'd0;
ir_valid <= 1'd0;
@@ -157,7 +157,7 @@ localparam BDATA_PC = 2'b01;
localparam BDATA_S4 = 2'b10;
localparam BDATA_S8 = 2'b11;
reg [RWIDTH-1:0]bdata_mux;
-always @(*) begin
+always_comb begin
case (do_sel_bdata)
BDATA_RB: bdata_mux = regs_bdata;
BDATA_PC: bdata_mux = pc;
@@ -171,7 +171,7 @@ localparam WSEL_RB = 2'b01;
localparam WSEL_OP = 2'b10;
localparam WSEL_LR = 2'b11;
reg [3:0]wsel_mux;
-always @(*) begin
+always_comb begin
case (do_sel_wsel)
WSEL_RA: wsel_mux = ir[7:4];
WSEL_RB: wsel_mux = ir[11:8];
@@ -185,7 +185,7 @@ localparam ALU_MHI = 2'b01;
localparam ALU_FN_HI = 2'b10;
localparam ALU_FN_LO = 2'b11;
reg [3:0]alu_op_mux;
-always @(*) begin
+always_comb begin
case (do_sel_alu_op)
ALU_MOV: alu_op_mux = 4'b0000;
ALU_MHI: alu_op_mux = 4'b0111;
@@ -214,7 +214,7 @@ assign debug_data = regs_adata;
assign debug_wr = do_fetch & ir_valid & (ir[15:12] == 4'b0010) & (ir[3:0] == 4'b1110);
`endif
-always @(*) begin
+always_comb begin
// decode stage
do_fetch = 1'b1;
do_load = 1'b0;
@@ -327,7 +327,7 @@ always @(*) begin
endcase
end
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
alu_op <= alu_op_mux;
adata <= regs_adata;
bdata <= bdata_mux;
diff --git a/tests/000_load_registers.s b/tests/000-load-registers.s
diff --git a/tests/001_simple_loop.s b/tests/001-simple-loop.s
diff --git a/tests/002-simple-math.s b/tests/002-simple-math.s
@@ -0,0 +1,21 @@
+ mov r0, 0
+ add r1, r0, 1
+ add r2, r0, 2
+ add r3, r1, 1
+ add r4, r3, 1
+
+ mov r15, 0
+ nop
+
+ sw r0, [r15]
+ sw r1, [r15]
+ sw r2, [r15]
+ sw r3, [r15]
+ sw r4, [r15]
+ word 0xffff
+
+;0000 0000
+;0000 0001
+;0000 0002
+;0000 0002
+;0000 0003
diff --git a/tests/003-increment.s b/tests/003-increment.s
@@ -0,0 +1,13 @@
+ mov r0, 0
+ add r0, r0, 1
+ add r0, r0, 1
+ add r0, r0, 1
+ add r0, r0, 1
+
+ mov r15, 0
+ nop
+
+ sw r0, [r15]
+ word 0xffff
+
+;0000 0004
diff --git a/tests/004-write-loop.s b/tests/004-write-loop.s
@@ -0,0 +1,25 @@
+ mov r15, 0x100
+ mov r14, 0x108
+ mov r0, 0xabcd
+
+loop:
+ slt r1, r15, r14
+ bnz r1, done
+ sw r0, [r15]
+ add r15, r15, 1
+ nop
+ b loop
+
+done:
+ word 0xffff
+
+
+;0100 abcd
+;0101 abcd
+;0102 abcd
+;0103 abcd
+;0104 abcd
+;0105 abcd
+;0106 abcd
+;0107 abcd
+;0100 0000
