commit 5264404e91c4b739d52e74fc650f16aeeb71e798
parent 2d62a08faff524d83f58c622e0e17b986c7d0e97
Author: Brian Swetland <swetland@frotz.net>
Date: Mon, 27 Feb 2023 18:37:22 -0800
headers for arm v7 debug and system control registers
Diffstat:
2 files changed, 166 insertions(+), 0 deletions(-)
diff --git a/src/arm-v7-debug.h b/src/arm-v7-debug.h
@@ -0,0 +1,92 @@
+// Copyright 2023, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+#pragma once
+
+// see: ARM v7-M Architecture Reference, C1
+// see: ARM v6-M Architecture Reference, C1
+
+#define DHCSR 0xE000EDF0 // RW Debug Halting Control/Status
+#define DCRSR 0xE000EDF4 // WO Debug Core Register Selector
+#define DCRDR 0xE000EDF8 // RW Debug Core Register Data
+#define DEMCR 0xE000EDFC // RW Debug Exception & Monitor Control
+
+
+// lower 16 bits are RW and have various restrictions
+// Enable Halting Debug
+// - cannot be modified by software, only DAP
+// - if changing from 0 to 1, C_MASKINTS must be written as 0
+// - 0 after power on reset
+#define DHCSR_C_DEBUGEN 0x00000001
+
+// Halt the Processor
+// - state unknown when C_DEBUGEN is 0
+#define DHCSR_C_HALT 0x00000002
+
+// Enable Single Step
+// - state unknown when C_DEBUGEN is 0
+#define DHCSR_C_STEP 0x00000004
+
+// mask PendSV, SysTick, and external interrupts
+// - if C_HALT is not 1, writes are unpredictable
+// - if C_MASKINTS is modified C_HALT must be written as 1
+// or results are unpredictable
+#define DHCSR_C_MASKINTS 0x00000008 // mask PenSV, SysTick, and Ext IRQs
+
+// (v7M) Allow imprecise debug entry
+// - can force stalled load/stores to complete
+// - unpredictable if C_DEBUGEN and C_HALT are not also set to 1
+// - make memory subsystem unpredictable when set:
+// debugger must reset processor before leaving debug
+#define DHCSR_C_SNAPSTALL 0x00000020 // (v7M) allow imprecise debug entry
+
+// magic value must be written to modify the above bits
+#define DHCSR_DBGKEY 0xA05F0000
+
+// upper 16 bits are RO
+#define DHCSR_S_REGRDY 0x00010000 // 0 on write to DCRSR, 1 when xfer done
+#define DHCSR_S_HALT 0x00020000 // 1 if cpu halted (in debug)
+#define DHCSR_S_SLEEP 0x00040000 // 1 when cpu sleeping
+#define DHCSR_S_LOCKUP 0x00080000 // 1 if cpu locked up (cleared on debug entry)
+#define DHCSR_S_RETIRE_ST 0x01000000 // 1 if instruction retired since last read
+#define DHCSR_S_RESET_ST 0x02000000 // 1 if cpu reset since last read
+
+
+// bit 16 controls read vs write
+#define DCRSR_RD 0x00000000
+#define DCRSR_WR 0x00010000
+
+// to write: write value to DCRDR
+// write (regno | DCRSR_WR) to DCRSR
+// poll DHCSR until S_REGRDY is 1
+//
+// to read: write (regno | DCRSR_RD) to DCRSR
+// poll DHCSR until S_REGRDY is 1
+// read value from DCRDR
+
+// 0..15 R0..R12,SP,LR,DebugReturnAddr
+// 16 xPSR
+// 17 MSP
+// 18 PSP
+// 20 CONTROL | PRIMASK (v6M)
+
+// 20 CONTROL | FAULTMASK | BASEPRI | PRIMASK (v7M)
+// 33 FPSCR (v7M w/ FPU)
+// 64..95 S0..S31 (v7M w/ FPU)
+
+
+#define DEMCR_VC_CORERESET 0x00000001 // Halt on Reset Vector *
+#define DEMCR_VC_MMERR 0x00000010 // Halt on MemManage exception
+#define DEMCR_VC_NOCPERR 0x00000020 // Halt on UsageFault for coproc access
+#define DEMCR_VC_CHKERR 0x00000040 // Halt on UsageFault for checking errors
+#define DEMCR_VC_STATERR 0x00000080 // Halt on UsageFault for state errors
+#define DEMCR_VC_BUSERR 0x00000100 // Halt on BusFault
+#define DEMCR_VC_INTERR 0x00000200 // Halt on exception entry/return faults
+#define DEMCR_VC_HARDERR 0x00000400 // Halt on HardFault *
+#define DEMCR_MON_EN 0x00010000
+#define DEMCR_MON_PEND 0x00020000
+#define DEMCR_MON_STEP 0x00040000
+#define DEMCR_MON_REQ 0x00080000
+#define DEMCR_TRCENA 0x01000000 // Enable DWT and ITM *
+// v6M only has *'d bits
+
diff --git a/src/arm-v7-system-control.h b/src/arm-v7-system-control.h
@@ -0,0 +1,74 @@
+// Copyright 2023, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+#pragma once
+
+// see: ARM v7-M Architecture Reference, B3.2
+// see: ARM v6-M Architecture Reference, B3.2
+
+#define CPUID 0xE000ED00 // RO CPUID Base *
+#define ICSR 0xE000ED04 // RW Interrupt Control/State *
+#define VTOR 0xE000ED08 // RW Vector Table Offset *
+#define AIRCR 0xE000ED0C // RW App Interrupt/Reset Control *
+#define SCR 0xE000ED10 // RW System Control Register *
+#define CCR 0xE000ED14 // RW Configuration & Control *
+#define SHPR1 0xE000ED18 // RW System Handler Priority 1
+#define SHPR2 0xE000ED1C // RW System Handler Priority 2 *
+#define SHPR3 0xE000ED20 // RW System Handler Priority 3 *
+#define SHCSR 0xE000ED24 // RW System Handler Control/State *
+#define CFSR 0xE000ED28 // RW Configurable Fault Status
+#define DFSR 0xE000ED30 // RW Debug Fault Status *
+#define HFSR 0xE000ED2C // RW HardFault Status
+#define MMFAR 0xE000ED34 // RW MemManage Fault Address
+#define BFAR 0xE000ED38 // RW BusFault Address
+#define AFSR 0xE000ED3C // RW Aux Fault Status
+// v6M has only *'d registers
+
+// DFSR bits indicate debug events, are R/W1C
+#define DFSR_HALTED 0x00000001
+#define DFSR_BKPT 0x00000002
+#define DFSR_DWTTRAP 0x00000004
+#define DFSR_VCATCH 0x00000008
+#define DFSR_EXTERNAL 0x00000010
+
+#define SHCSR_MEMFAULTACT 0x00000001
+#define SHCSR_BUSFAULTACT 0x00000002
+#define SHCSR_USGFAULTACT 0x00000008
+#define SHCSR_SVCALLACT 0x00000080
+#define SHCSR_MONITORACT 0x00000100
+#define SHCSR_PENDSVACT 0x00000400
+#define SHCSR_SYSTICKACT 0x00000800
+#define SHCSR_USGFAULTPENDED 0x00001000
+#define SHCSR_MEMFAULTPENDED 0x00002000
+#define SHCSR_BUSFAULTPENDED 0x00004000
+#define SHCSR_SVCALLPENDED 0x00008000 // *
+#define SHCSR_MEMFAULTENA 0x00010000
+#define SHCSR_BUSFAULTENA 0x00020000
+#define SHCSR_USGFAULTENA 0x00040000
+
+#define HFSR_VECTTBL 0x00000002
+#define HFSR_FORCED 0x40000000
+#define HFSR_DEBUGEVT 0x80000000
+
+#define SCR_SLEEPONEXIT 0x00000002
+#define SCR_SLEEPDEEP 0x00000004
+#define SCR_SEVONPEND 0x00000010
+
+#define CCR_NONBASETHRDENA 0x00000001 // Enter Thread Mode w/ Exception Active Enable
+#define CCR_USESETMPEND 0x00000002 // Unpriv Access to STIR Enable
+#define CCR_UNALIGN_TRP 0x00000008 // Unaligned Access Trap Enable *
+#define CCR_DIV_0_TRP 0x00000010 // Divide By Zero Trap Enable
+#define CCR_BFHFNMIGN 0x00000100 // Ignore Precise Data Faults at Prio -1 & -2
+#define CCR_STKALIGN 0x00000200 // 8 byte Stack Alignment *
+#define CCR_DC 0x00010000 // Data & Unified Cache Enable
+#define CCR_IC 0x00020000 // Instruction Cache Enabel
+#define CCR_BP 0x00040000 // Branch Prediction Enable
+
+#define AIRCR_VECTKEY 0x05FA0000 // reads back as 0xFA050000 on v7M
+#define AIRCR_PRIGROUP_MASK 0x00000700 //
+#define AIRCR_BIG_ENDIAN 0x00008000 // *
+#define AIRCR_SYSRESETREQ 0x00000004 // system reset request *
+#define AIRCR_VECTCLRACTIVE 0x00000002 // clear exception state @ *
+#define AIRCR_VECTRESET 0x00000001 // request local reset @
+
+// @ unpredictable if processor not in debug halt
