zynq-sandbox

commit 1e47ff51029e8e88b64a4caecd76b5e8c4cb8806
parent 7944b5fbac8e3ccf15bf62b06d0cbe70e302e22e
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun, 27 Jul 2014 22:29:01 -0700

axi-dma-writer: don't advance input unless *complete* wdata handshake occurs

Diffstat:
M
hdl/axi_dma_writer.sv
 | 
2
+-

1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hdl/axi_dma_writer.sv b/hdl/axi_dma_writer.sv
@@ -60,7 +60,7 @@ reg busy_next;
 wire count_is_zero = (count == 4'h0);
 wire count_is_one = (count == 4'h1);
 
-assign advance = m.wready & busy;
+assign advance = m.wvalid & m.wready & busy;
 
 always_comb begin
 	state_next = state;