commit 7944b5fbac8e3ccf15bf62b06d0cbe70e302e22e
parent f2bcfc5010e64d943e70f158103092b7a38834fc
Author: Brian Swetland <swetland@frotz.net>
Date: Sun, 27 Jul 2014 22:20:27 -0700
zybo-eth-capture: simple packet capture to axi test (not working yet)
FIFO18E1 fifos seem to be working a bit differently on the fpga than in simulation...
Diffstat:
4 files changed, 170 insertions(+), 8 deletions(-)
diff --git a/Makefile b/Makefile
@@ -76,6 +76,22 @@ MODULE_SRCS += hdl/axi_sram.sv
#include build/verilator-sim.mk
include build/vivado-xsim.mk
+MODULE_NAME := zybo-eth-capture
+MODULE_PART := xc7z010clg400-1
+MODULE_SRCS := hdl/zybo_eth_capture.sv
+MODULE_SRCS += hdl/zynq_ps_1m_1s.sv
+MODULE_SRCS += hdl/mmcm_1in_3out.sv
+MODULE_SRCS += hdl/eth_capture.sv
+MODULE_SRCS += hdl/eth_rmii_rx.sv
+MODULE_SRCS += hdl/pkt_bytes_to_words.sv
+MODULE_SRCS += hdl/xilinx_async_fifo.sv
+MODULE_SRCS += hdl/sync_oneway.sv
+MODULE_SRCS += hdl/axi_ifc.sv
+MODULE_SRCS += hdl/axi_dma_writer.sv
+MODULE_SRCS += hdl/axi_registers.sv
+MODULE_SRCS += hdl/zybo_eth.xdc
+include build/vivado-bitfile.mk
+
MODULE_NAME := zybo-eth
MODULE_PART := xc7z010clg400-1
MODULE_SRCS := hdl/zybo_eth.sv
diff --git a/hdl/eth_capture.sv b/hdl/eth_capture.sv
@@ -25,9 +25,19 @@ module eth_capture(
// interface to axi
input clk,
input reset,
- axi_ifc axi_dma
+ input enable,
+ axi_ifc.master axi_dma
);
+parameter BASE_ADDR = 32'h10000000;
+
+wire active;
+sync_oneway sync_enable(
+ .txclk(clk),
+ .txdat(enable),
+ .rxclk(clk50),
+ .rxdat(active)
+ );
wire [31:0]w_data;
wire w_valid;
@@ -46,8 +56,8 @@ end
pkt_bytes_to_words cap0(
.clk(clk50),
.rxdata(rxdata),
- .rxvalid(rxvalid),
- .rxeop(rxeop),
+ .rxvalid(rxvalid & active),
+ .rxeop(rxeop & active),
.data(w_data),
.bytecount(bytecount),
.eop(w_eop),
@@ -144,7 +154,7 @@ end
reg fifo_reset = 0;
wire [31:0]dfifo_data;
-reg dfifo_rd = 0;
+wire dfifo_rd;
wire dfifo_empty;
wire dfifo_active;
@@ -206,10 +216,12 @@ wire dma_start = (~cfifo_empty) & (~dma_busy);
wire dma_busy;
always @(posedge clk) begin
- if (dma_start) begin
- cfifo_rd <= 1;
- end else begin
- cfifo_rd <= 0;
+ if (cfifo_active & dfifo_active) begin
+ if (dma_start) begin
+ cfifo_rd <= 1;
+ end else begin
+ cfifo_rd <= 0;
+ end
end
end
diff --git a/hdl/test/eth_capture_test.sv b/hdl/test/eth_capture_test.sv
@@ -72,6 +72,7 @@ eth_capture cap0(
.rxvalid(rxvalid),
.clk(clk),
.reset(cap_reset),
+ .enable(1),
.axi_dma(axi_dma)
);
diff --git a/hdl/zybo_eth_capture.sv b/hdl/zybo_eth_capture.sv
@@ -0,0 +1,133 @@
+// Copyright 2014 Brian Swetland <swetland@frotz.net>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`timescale 1ns / 1ps
+
+module top(
+ input clk,
+ output [3:0]led,
+
+ output phy0_mdc,
+ //output phy0_mdio,
+ output phy0_clk,
+ output phy0_txen,
+ output [1:0]phy0_tx,
+ input phy0_crs,
+ input [1:0]phy0_rx
+ );
+
+assign led = 0;
+
+wire clk50;
+
+mmcm_1in_3out #(
+ .CLKIN_PERIOD(8.0),
+ .VCO_MUL(8.000),
+ .VCO_DIV(1),
+ .OUT0_DIV(20.000),
+ .OUT1_DIV(10),
+ .OUT2_DIV(10)
+ ) mmcm0 (
+ .i_clk(clk),
+ .o_clk0(clk50),
+ .o_clk1(),
+ .o_clk2()
+ );
+
+assign phy0_clk = clk50;
+assign phy0_mdc = 1;
+
+wire [7:0]rxdata;
+wire rxvalid;
+wire rxeop;
+wire rxsop;
+
+(* keep_hierarchy = "yes" *)
+eth_rmii_rx phy0rx(
+ .clk50(clk50),
+ .rx(phy0_rx),
+ .crs_dv(phy0_crs),
+ .data(rxdata),
+ .valid(rxvalid),
+ .eop(rxeop),
+ .sop(rxsop),
+ .out_tx(),
+ .out_txen()
+ );
+
+axi_ifc #(.IWIDTH(12),.AXI3(1)) axi_ctl();
+axi_ifc #(.IWIDTH(6),.AXI3(1)) axi_dma0();
+
+zynq_ps7 zynq(
+ .fclk0(),
+ .m_axi_gp0_clk(clk),
+ .m_axi_gp0(axi_ctl),
+ .s_axi_gp0_clk(clk),
+ .s_axi_gp0(axi_dma0)
+ );
+
+reg cap_enable = 0;
+reg cap_reset = 0;
+
+eth_capture #(
+ .BASE_ADDR(32'h10000000)
+ ) cap0 (
+ .clk50(clk50),
+ .rxsop(rxsop),
+ .rxeop(rxeop),
+ .rxdata(rxdata),
+ .rxvalid(rxvalid),
+ .clk(clk),
+ .reset(cap_reset),
+ .enable(cap_enable),
+ .axi_dma(axi_dma0)
+ );
+
+wire wr;
+wire [31:0]wdata;
+
+wire rrd;
+wire [1:0]rreg;
+reg [31:0]rdata = 0;
+
+always_ff @(posedge clk) begin
+ if (rrd) case(rreg)
+ 0: rdata <= 32'haabbccdd;
+ 1: rdata <= 0;
+ 2: rdata <= 0;
+ 3: rdata <= 0;
+ endcase
+end
+
+axi_registers regs(
+ .clk(clk),
+ .s(axi_ctl),
+ .o_rreg(rreg),
+ .o_wreg(),
+ .i_rdata(rdata),
+ .o_wdata(wdata),
+ .o_rd(rrd),
+ .o_wr(wr)
+ );
+
+always @(posedge clk) begin
+ if (wr) begin
+ cap_enable <= wdata[0];
+ cap_reset <= wdata[1];
+ end else begin
+ cap_reset <= 0;
+ end
+end
+
+endmodule
