zynq-sandbox

commit 48c978e056122f8ee522d2e51244994b31f34543
parent 2f754e06967886118e7af8511deeb08c4663277a
Author: Brian Swetland <swetland@frotz.net>
Date:   Thu, 28 Aug 2014 00:07:17 -0700

sync_oneway: annotate so xilinx tools handle optimally

Diffstat:
M
hdl/sync_oneway.sv
 | 
9
++++++++-

1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hdl/sync_oneway.sv b/hdl/sync_oneway.sv
@@ -22,7 +22,14 @@ module sync_oneway(
 	output rxdat
 	);
 
-reg a = 0, b = 0, c = 0;
+reg a = 0;
+
+// Mark as ASYNC_REG to ensure they are not optimized away, are adjacent
+// (same slice), and inform // xilinx simulation tools that they're being
+// used for synchronization.
+// See UG912 Vivado Properties
+(* ASYNC_REG = "TRUE" *)
+reg b = 0, c = 0;
 
 always_ff @(posedge txclk)
 	a <= txdat;