zynq-sandbox

commit 4df259abac810216edf3714588fae32d5bc3802b
parent 28bd35693d901be808e65669eca69f49fd28135f
Author: Brian Swetland <swetland@frotz.net>
Date:   Sat, 26 Jul 2014 23:13:45 -0700

eth-rmii-test: support xsim as well as verilator

Diffstat:
M
hdl/test/eth_rmii_test.sv
 | 
6
++++++

1 file changed, 6 insertions(+), 0 deletions(-)
diff --git a/hdl/test/eth_rmii_test.sv b/hdl/test/eth_rmii_test.sv
@@ -15,7 +15,13 @@
 
 `timescale 1ns / 1ps
 
+`ifdef verilator
 module testbench(input clk);
+`else
+module testbench();
+reg clk = 0;
+always #5 clk = ~clk;
+`endif
 
 // RMII transport between tx and rx
 wire [1:0]eth_data;