commit 50d2d54e38075aef416dbaf0ff539319159a3ae4
parent f6320df08ad191206ec7903c0a778f5779fcd2bf
Author: Brian Swetland <swetland@frotz.net>
Date: Sun, 5 Oct 2014 02:49:35 -0700
README: update some stuff
Diffstat:
| M | README | | | 21 | ++++++++++++++------- |
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/README b/README
@@ -4,7 +4,7 @@ with the Xilinx Zynq SoC FPGA, particularly around using a commandline
workflow and avoiding the IPI (IP Integrator) workflow.
An earlier version that attempted to make use of IPI from the commandline
-lives in the deprecated-v0 branch.
+lives in the deprecated-ipi branch.
Warning: This is very much a work in progress.
@@ -12,6 +12,8 @@ Projects
--------
zybo-hdmi - display a test pattern ZYBO board's HDMI output
zybo-hdmi-axi - same, but add an axi slave to adjust the pattern
+zybo-simple-io - AXI access to the switches, buttons, and LEDs
+...
Repository Layout
-----------------
@@ -20,8 +22,8 @@ build/... - makefiles and tcl scripts
Generated Files
---------------
-ip/${name}/... - where Vivado IP packages are generated
sim/${name}-vsim/... - where Verilator intermediates are generated
+sim/${name}-xsim/... - where Xilinx Xsim intermediates are generated
synth/${name}/... - where Vivado synthesis intermediates are generated
out/... - where FPGA final products (bitfiles/etc) end up
out/${name}.bit - bitfile for project name
@@ -36,17 +38,22 @@ MODULE_SRCS := ...
2. invoke the appropriate build rules for the module type:
+include build/vivado-bitfile.mk
+ - create Xilinx out/$(MODULE_NAME).bit bitfile
+ - target device MODULE_PART
+ - required: a top level module named top
+ - to build: make modulename
+
include build/verilator-sim.mk
- create Verilator simulation target
- required: a top level module named testbench(input clk)
- provided: clock signal
- to run: make modulename-vsim
-include build/vivado-bitfile.mk
- - create Xilinx out/$(MODULE_NAME).bit bitfile
- - target device MODULE_PART
- - required: a top level module named top
- - to build: make modulename
+include build/vivado-xsim.mk
+ - create Vivado Xsim simulation target
+ - required: a top level module named testbench
+ - to run: make modulename-xsim
Tools
-----
