zynq-sandbox

commit f6320df08ad191206ec7903c0a778f5779fcd2bf
parent 2b248574a0cbeb16af03b0f76f36fae59ba6eec2
Author: Brian Swetland <swetland@frotz.net>
Date:   Wed,  1 Oct 2014 18:05:54 -0700

build: allow Makefile to specify build directory (relative) location

Diffstat:
M
build/init.mk
 | 
2
++
M
build/verilator-sim.mk
 | 
2
+-
M
build/vivado-bitfile.mk
 | 
4
++--

3 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/build/init.mk b/build/init.mk
@@ -21,3 +21,5 @@ endif
 
 ALL_TARGETS :=
 
+# default: assume build is adjacent to top level Makefile
+BUILD ?= build
diff --git a/build/verilator-sim.mk b/build/verilator-sim.mk
@@ -18,7 +18,7 @@ MODULE_VLG_SRCS := $(filter-out %.hex,$(MODULE_SRCS))
 MODULE_OPTS := --top-module testbench 
 #-Ihdl
 MODULE_OPTS += --Mdir $(MODULE_OBJDIR)
-MODULE_OPTS += --exe ../../build/testbench.cpp
+MODULE_OPTS += --exe ../../$(BUILD)/testbench.cpp
 MODULE_OPTS += --cc
 MODULE_OPTS += -DSIMULATION
 
diff --git a/build/vivado-bitfile.mk b/build/vivado-bitfile.mk
@@ -44,7 +44,7 @@ $(MODULE_BIT): $(MODULE_HEX_SRCS) $(MODULE_CFG)
 	@mkdir -p $(_DIR) out
 	@rm -f $(_DIR)/log.txt
 	@for hex in $(_HEX) ; do cp $$hex $(_DIR) ; done
-	@(cd $(_DIR) && $(VIVADO) -mode batch -log log.txt -nojournal -source ../../build/build-bitfile.tcl)
+	@(cd $(_DIR) && $(VIVADO) -mode batch -log log.txt -nojournal -source ../../$(BUILD)/build-bitfile.tcl)
 
 $(MODULE_NAME)-rtl: _HEX := $(MODULE_HEX_SRCS)
 $(MODULE_NAME)-rtl: _DIR := $(MODULE_OBJDIR)
@@ -54,7 +54,7 @@ $(MODULE_NAME)-rtl: $(MODULE_HEX_SRCS) $(MODULE_CFG)
 	@mkdir -p $(_DIR) out
 	@rm -f $(_DIR)/log.txt
 	@for hex in $(_HEX) ; do cp $$hex $(_DIR) ; done
-	@(cd $(_DIR) && $(VIVADO) -log log.rtl.txt -nojournal -source ../../build/elaborate-design.tcl)
+	@(cd $(_DIR) && $(VIVADO) -log log.rtl.txt -nojournal -source ../../$(BUILD)/elaborate-design.tcl)
 
 $(MODULE_NAME): $(MODULE_BIT)