zynq-sandbox

commit afd31761620536c7c064b9926f12ae748e896602
parent ac2c6fb4cb2cf02d5c056513fa9ba2056f2df085
Author: Brian Swetland <swetland@frotz.net>
Date:   Mon, 19 Nov 2018 09:09:03 -0800

update software versions (vivado 2014.3 -> 2018.2), small fixes

nexys4.sv had some unconnected ports that verilator disliked

Diffstat:
M
build/init.mk
 | 
6
+++---
M
hdl/nexys4.sv
 | 
5
++++-

2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/build/init.mk b/build/init.mk
@@ -3,10 +3,10 @@
 ## Licensed under the Apache License, Version 2.0 
 ## http://www.apache.org/licenses/LICENSE-2.0
 
-VERILATOR := VERILATOR_ROOT=/work/verilator /work/verilator/bin/verilator
+VERILATOR := verilator
 
-VIVADOPATH := /work/xilinx/Vivado/2014.3
-XSDKPATH := /work/xilinx/SDK/2014.3
+VIVADOPATH := /work/xilinx/Vivado/2018.2
+XSDKPATH := /work/xilinx/SDK/2018.2
 
 VIVADO := $(VIVADOPATH)/bin/vivado
 XELAB := $(VIVADOPATH)/bin/xelab
diff --git a/hdl/nexys4.sv b/hdl/nexys4.sv
@@ -74,7 +74,10 @@ eth_rmii_rx phy0rx(
 	.crs_dv(phy0_crs),
 	.data(rxdata),
 	.valid(rxvalid),
-	.eop(rxeop)
+	.eop(rxeop),
+	.out_tx(),
+	.out_txen(),
+	.sop()
 	);
 
 wire go;