commit f72171549f00e9d39f138f23904f447718b1685e parent 495ebc364d6b96d285c23e58bfc909bdbaa90fa2 Author: Brian Swetland <swetland@frotz.net> Date: Fri, 4 Jul 2014 11:21:47 -0700 zybo-hdmi-axi: add constraints for 100MHz fclk0 Diffstat:
| M | Makefile | | | 1 | + |
| A | hdl/zybo_hdmi_fclk.xdc | | | 6 | ++++++ |
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile @@ -20,6 +20,7 @@ MODULE_SRCS += $(HDMI_SRCS) MODULE_SRCS += hdl/chardata8x8.hex MODULE_SRCS += hdl/textdisplay.sv MODULE_SRCS += hdl/zybo_hdmi.xdc +MODULE_SRCS += hdl/zybo_hdmi_fclk.xdc include build/vivado-bitfile.mk MODULE_NAME := zybo-hdmi diff --git a/hdl/zybo_hdmi_fclk.xdc b/hdl/zybo_hdmi_fclk.xdc @@ -0,0 +1,6 @@ + +create_clock -name clk_fpga_0 -period "10.00" [get_pins "zynq/ps7_i/FCLKCLK[0]"] +set_input_jitter clk_fpga_0 0.3 + +set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks sys_clk_pin] -group clk_fpga_0 +