commit e3a11f9b0d1d14b9759b421ef54e0f5c9519037a
parent 758ac5a8f749d2e36edc7bad88afd03f5733a8d0
Author: Brian Swetland <swetland@frotz.net>
Date: Thu, 16 Feb 2012 01:10:59 -0800
vga: add 640x480 vga peripheral w/ 40x30 character display
Diffstat:
| A | verilog/chardata.v | | | 143 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | verilog/prom.txt | | | 1024 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | verilog/vga.v | | | 97 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | verilog/videoram.v | | | 25 | +++++++++++++++++++++++++ |
| A | verilog/vram.txt | | | 2048 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
5 files changed, 3337 insertions(+), 0 deletions(-)
diff --git a/verilog/chardata.v b/verilog/chardata.v
@@ -0,0 +1,143 @@
+// Copyright 2012, Brian Swetland
+//
+// Pixel Data Reader / Character Data Reader
+//
+// assert newline and provide line address to start linefetch
+// character data will be provided on cdata two clocks later
+//
+// assert next to advance: character data will be provided two clocks later
+//
+// vram_addr/vram_data: connect to sync sram
+
+`timescale 1ns/1ns
+
+module pixeldata(
+ input clk,
+ input newline,
+ input advance,
+ input [7:0] line,
+
+ output reg [11:0] pixel,
+
+ input [7:0] vram_data,
+ output [10:0] vram_addr
+ );
+
+wire [7:0] new_cdata;
+reg next;
+
+chardata chardata(
+ .clk(clk),
+ .newline(newline),
+ .line(line),
+ .next(next),
+ .cdata(new_cdata),
+ .vram_data(vram_data),
+ .vram_addr(vram_addr)
+ );
+
+reg [7:0] cdata, next_cdata;
+reg [3:0] bitcount, next_bitcount;
+reg [1:0] state, next_state;
+
+always @(*) begin
+ next_bitcount = bitcount;
+ next_cdata = cdata;
+ next = 1'b0;
+
+ /* s0 machine is used to wait until the first cdata
+ * is ready after a newline signal, load that cdata,
+ * then enter the shift-out (s0=0) mode
+ */
+ case (state)
+ 2'h3: next_state = 2'h2;
+ 2'h2: next_state = 2'h1;
+ 2'h1: begin
+ next_state = 2'h0;
+ next_cdata = new_cdata;
+ end
+ 2'h0: begin
+ next_state = 2'h0;
+ if (advance)
+ next_bitcount = bitcount - 4'd1;
+ if (bitcount == 4'h4)
+ next = 1'b1;
+ if (bitcount == 4'h0)
+ next_cdata = new_cdata;
+ end
+ endcase
+
+ if (newline) begin
+ next_state = 2'h3;
+ next_bitcount = 4'hF;
+ end
+
+ pixel = (cdata[bitcount[3:1]] ? 12'hFFF : 12'h00F);
+end
+
+always @(posedge clk) begin
+ bitcount <= next_bitcount;
+ state <= next_state;
+ cdata <= next_cdata;
+end
+
+endmodule
+
+
+module chardata(
+ input clk,
+ input newline,
+ input next,
+ input [7:0] line,
+ output reg [7:0] cdata,
+
+ input [7:0] vram_data,
+ output reg [10:0] vram_addr
+ );
+
+`define SWAIT 2'h0
+`define SLOAD 2'h1
+`define SLATCH 2'h2
+
+reg [7:0] pattern_rom [0:1023];
+reg [2:0] pline, next_pline;
+
+reg [1:0] state, next_state;
+reg [10:0] next_addr;
+reg [7:0] next_cdata;
+
+initial $readmemh("prom.txt", pattern_rom);
+
+always @(*) begin
+ next_state = state;
+ next_addr = vram_addr;
+ next_cdata = cdata;
+ next_pline = pline;
+ if (newline) begin
+ next_state = `SLOAD;
+ next_addr = { line[7:3], 6'b0 };
+ next_pline = line[2:0];
+ end
+ case (state)
+ `SWAIT: if (next) begin
+ next_state = `SLOAD;
+ end
+ `SLOAD: begin
+ next_state = `SLATCH;
+ end
+ `SLATCH: begin
+ next_state = `SWAIT;
+ next_addr = vram_addr + 11'd1;
+ next_cdata = pattern_rom[{vram_data, pline}];
+ end
+ endcase
+end
+
+always @(posedge clk) begin
+ state <= next_state;
+ vram_addr <= next_addr;
+ cdata <= next_cdata;
+ pline <= next_pline;
+end
+
+endmodule
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diff --git a/verilog/vga.v b/verilog/vga.v
@@ -0,0 +1,97 @@
+// Copyright 2012, Brian Swetland
+
+`timescale 1ns/1ns
+
+// Vert: 2xSync 30xBack 480xData 12xFront -> 524 lines
+// Horz: 96xSync 48xBack 640xData 16xFront -> 800 pixels
+//
+// CLK: 25MHz, px=40nS, line=32uS, frame=16.768mS
+
+module vga(
+ input clk,
+ input reset,
+ output reg hs,
+ output reg vs,
+ output reg [3:0] r,
+ output reg [3:0] g,
+ output reg [3:0] b,
+
+ output reg newline,
+ output reg advance,
+ output reg [7:0] line,
+ input [11:0] pixel
+ );
+
+reg [9:0] hcount;
+reg [9:0] vcount;
+
+reg [9:0] next_hcount;
+reg [9:0] next_vcount;
+reg next_hs, next_vs;
+reg active;
+reg next_startline;
+reg [9:0] next_line;
+
+always @* begin
+ if (hcount == 10'd799) begin
+ if (vcount == 10'd523)
+ next_vcount = 10'd0;
+ else
+ next_vcount = vcount + 10'd1;
+ next_hcount = 10'd0;
+ end else begin
+ next_vcount = vcount;
+ next_hcount = hcount + 10'd1;
+ end
+
+ if (reset) begin
+ next_hcount = 10'd0;
+ next_vcount = 10'd0;
+ end
+
+ if (next_hcount == 0)
+ next_startline = 1'b1;
+ else
+ next_startline = 1'b0;
+
+ if (next_hcount < 10'd96)
+ next_hs = 1'b0;
+ else
+ next_hs = 1'b1;
+
+ if (next_vcount < 10'd2)
+ next_vs = 1'b0;
+ else
+ next_vs = 1'b1;
+
+ active = 1'b0;
+ if ((next_vcount > 31) && (next_vcount < 512))
+ if ((next_hcount > 143) && (next_hcount < 784))
+ active = 1'b1;
+
+ next_line = next_vcount - 10'd32;
+end
+
+always @(posedge clk) begin
+ hcount <= next_hcount;
+ vcount <= next_vcount;
+ hs <= next_hs;
+ vs <= next_vs;
+
+ /* signals to pixel generator */
+ newline <= next_startline;
+ advance <= active;
+ line <= next_line[8:1];
+
+ if (active) begin
+ r <= pixel[11:8];
+ g <= pixel[7:4];
+ b <= pixel[3:0];
+ end else begin
+ r <= 4'd0;
+ g <= 4'd0;
+ b <= 4'd0;
+ end
+end
+
+endmodule
diff --git a/verilog/videoram.v b/verilog/videoram.v
@@ -0,0 +1,25 @@
+// Copyright 2012, Brian Swetland. Use at your own risk.
+//
+// sync sram with independent read/write addressing
+
+`timescale 1ns/1ns
+
+module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) (
+ input clk, input we,
+ input [AWIDTH-1:0] waddr,
+ input [DWIDTH-1:0] wdata,
+ input [AWIDTH-1:0] raddr,
+ output reg [DWIDTH-1:0] rdata
+ );
+
+reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
+
+initial $readmemh("vram.txt", mem);
+
+always @ (posedge clk) begin
+ if (we)
+ mem[waddr] <= wdata;
+ rdata <= mem[raddr];
+end
+
+endmodule
diff --git a/verilog/vram.txt b/verilog/vram.txt
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