commit 37c5c9410964561e027fbf9959aead870922f05c
parent 091bc9509b42685ca76eb0b7584973bb901fadb5
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 15 Dec 2018 08:02:12 -0800
project: add cpu16-icebreaker-hdmi111 project
This enables the BML 3bit HDMI pmod on the 1B connector
Update vga plumbing to expose clock and active signals needed.
Diffstat:
8 files changed, 111 insertions(+), 0 deletions(-)
diff --git a/hdl/board_icebreaker_hdmi111.pcf b/hdl/board_icebreaker_hdmi111.pcf
@@ -0,0 +1,22 @@
+set_io clk12m_in 35
+
+# pmod1b
+set_io hdmi_clk 38
+set_io hdmi_hsync 34
+set_io hdmi_vsync 28
+set_io hdmi_de 32
+set_io hdmi_red 42
+set_io hdmi_grn 43
+set_io hdmi_blu 36
+
+set_io spi_miso 14
+set_io spi_mosi 17
+set_io spi_clk 15
+set_io spi_cs 16
+
+set_io uart_rx 6
+set_io uart_tx 9
+
+set_io led_red 11
+set_io led_grn 37
+
diff --git a/hdl/board_icebreaker_hdmi111.v b/hdl/board_icebreaker_hdmi111.v
@@ -0,0 +1,65 @@
+// Copyright 2018, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+module top(
+ input clk12m_in,
+ output hdmi_red,
+ output hdmi_grn,
+ output hdmi_blu,
+ output hdmi_hsync,
+ output hdmi_vsync,
+ output hdmi_de,
+ output hdmi_clk,
+ input uart_rx,
+ output uart_tx,
+ output led_red,
+ output led_grn
+ );
+
+wire hdmi_clk_src;
+
+`ifdef verilator
+assign hdmi_clk = hdmi_clk_src;
+`else
+SB_IO #(
+ .PIN_TYPE(6'b010000), // DDR OUTPUT
+ .PULLUP(1'b0),
+ .NEG_TRIGGER(1'b0),
+ .IO_STANDARD("SB_LVCMOS")
+ ) hdmi_clk_io (
+ .PACKAGE_PIN(hdmi_clk),
+ .LATCH_INPUT_VALUE(),
+ .CLOCK_ENABLE(), // per docs, leave discon for always enable
+ .INPUT_CLK(),
+ .OUTPUT_CLK(hdmi_clk_src),
+ .D_OUT_0(1'b1),
+ .D_OUT_1(1'b0),
+ .D_IN_0(),
+ .D_IN_1()
+ );
+`endif
+
+system_cpu16_vga40x30 #(
+ .BPP(1)
+ ) system (
+ .clk12m_in(clk12m_in),
+ .vga_red(hdmi_red),
+ .vga_grn(hdmi_grn),
+ .vga_blu(hdmi_blu),
+ .vga_hsync(hdmi_hsync),
+ .vga_vsync(hdmi_vsync),
+ .vga_active(hdmi_de),
+ .vga_clk(hdmi_clk_src),
+ .spi_mosi(),
+ .spi_miso(),
+ .spi_clk(),
+ .spi_cs(),
+ .uart_rx(uart_rx),
+ .uart_tx(uart_tx),
+ .led_red(led_red),
+ .led_grn(led_grn),
+ .out1(),
+ .out2()
+ );
+
+endmodule
diff --git a/hdl/board_icebreaker_vga444.v b/hdl/board_icebreaker_vga444.v
@@ -25,6 +25,8 @@ system_cpu16_vga40x30 #(
.vga_blu(vga_blu),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
+ .vga_active(),
+ .vga_clk(),
.spi_mosi(),
.spi_miso(),
.spi_clk(),
diff --git a/hdl/board_lattice_evb.v b/hdl/board_lattice_evb.v
@@ -25,6 +25,8 @@ system_cpu16_vga40x30 #(
.vga_blu(vga_blu),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
+ .vga_active(),
+ .vga_clk(),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_clk(spi_clk),
diff --git a/hdl/system_cpu16_vga40x30.v b/hdl/system_cpu16_vga40x30.v
@@ -14,6 +14,8 @@ module system_cpu16_vga40x30 #(
output [BPP-1:0]vga_blu,
output vga_hsync,
output vga_vsync,
+ output vga_active,
+ output vga_clk,
input spi_mosi,
output spi_miso,
input spi_clk,
@@ -180,12 +182,15 @@ vga40x30x2 #(
.hs(vga_hsync),
.vs(vga_vsync),
.fr(),
+ .active(vga_active),
.vram_waddr(waddr[10:0]),
.vram_wdata(wdata[7:0]),
.vram_we(we & w_cs_vram),
.vram_clk(sys_clk)
);
+assign vga_clk = clk25m;
+
// hack: flip display from blue to red when CPU is held in reset
assign vga_red = cpu_reset ? vb : vr;
assign vga_grn = vg;
diff --git a/hdl/testvga.sv b/hdl/testvga.sv
@@ -27,6 +27,7 @@ vga40x30x2 vga(
.hs(vga_hsync),
.vs(vga_vsync),
.fr(vga_frame),
+ .active(),
.vram_waddr(11'b0),
.vram_wdata(8'b0),
.vram_we(1'b0),
diff --git a/hdl/vga/vga40x30x2.v b/hdl/vga/vga40x30x2.v
@@ -11,6 +11,7 @@ module vga40x30x2 #(
output hs,
output vs,
output fr,
+ output active,
input vram_clk,
input [10:0]vram_waddr,
input [7:0]vram_wdata,
@@ -38,6 +39,8 @@ vga #(
.pixel(pixel)
);
+assign active = advance;
+
wire [10:0]vram_raddr;
wire [7:0]vram_rdata;
diff --git a/project/cpu16-icebreaker-hdmi111.def b/project/cpu16-icebreaker-hdmi111.def
@@ -0,0 +1,11 @@
+
+PROJECT_TYPE := nextpnr-ice40
+
+PROJECT_SRCS := hdl/board_icebreaker_hdmi111.v hdl/board_icebreaker_hdmi111.pcf
+PROJECT_SRCS += hdl/system_cpu16_vga40x30.v hdl/lattice/pll_12_25.v
+#PROJECT_SRCS += hdl/spi_debug_ifc.v
+PROJECT_SRCS += hdl/uart_debug_ifc.sv hdl/uart_rx.sv hdl/crc8_serial.sv
+PROJECT_SRCS += hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
+PROJECT_SRCS += hdl/cpu16.sv hdl/cpu16_regs.sv hdl/cpu16_alu.sv
+
+PROJECT_NEXTPNR_OPTS := --package sg48 --up5k
