commit 667cf5d1b948c4eae5fb951af4530a337d2e8388
parent d71be0492153b0183f7a86d7a9b5817f95c60157
Author: Brian Swetland <swetland@frotz.net>
Date: Wed, 30 Dec 2015 20:07:21 -0800
updated top file, constrains and pll config for ICE40Ultra dev board
Diffstat:
4 files changed, 158 insertions(+), 28 deletions(-)
diff --git a/hdl/ice40.pcf b/hdl/ice40.pcf
@@ -0,0 +1,18 @@
+set_io clk12m C2 -io_std SB_LVCMOS -pullup no
+
+set_io vga_b[0] D6 -io_std SB_LVCMOS -pullup no
+set_io vga_b[1] D5 -io_std SB_LVCMOS -pullup no
+set_io vga_g[0] E3 -io_std SB_LVCMOS -pullup no
+set_io vga_g[1] F3 -io_std SB_LVCMOS -pullup no
+set_io vga_hsync E5 -io_std SB_LVCMOS -pullup no
+set_io vga_r[0] F6 -io_std SB_LVCMOS -pullup no
+set_io vga_r[1] F5 -io_std SB_LVCMOS -pullup no
+set_io vga_vsync E6 -io_std SB_LVCMOS -pullup no
+
+set_io spi_miso F2 -io_std SB_LVCMOS -pullup no
+set_io spi_mosi D1 -io_std SB_LVCMOS -pullup no
+set_io spi_clk E1 -io_std SB_LVCMOS -pullup no
+set_io spi_cs F1 -io_std SB_LVCMOS -pullup no
+
+set_io out1 B1 -io_std SB_LVCMOS -pullup no
+set_io out2 B2 -io_std SB_LVCMOS -pullup no
diff --git a/hdl/ice40.sdc b/hdl/ice40.sdc
@@ -0,0 +1,5 @@
+
+create_clock -period 83.333 -name {clk12m} [get_ports {clk12m}]
+
+create_clock -period 166.666 -name {x_clk} [get_ports {x_clk}]
+
diff --git a/hdl/ice40.v b/hdl/ice40.v
@@ -4,60 +4,126 @@
`timescale 1ns / 1ps
module top(
- input clk,
- output [15:0]trace
+ input clk12m,
+ output [1:0]vga_r,
+ output [1:0]vga_g,
+ output [1:0]vga_b,
+ output vga_hsync,
+ output vga_vsync,
+ input spi_mosi,
+ output spi_miso,
+ input spi_clk,
+ input spi_cs,
+ output out1,
+ output out2
);
-wire [15:0]waddr /* synthesis syn_keep=1 */;
-wire [15:0]wdata /* synthesis syn_keep=1 */;
-wire we /* synthesis syn_keep=1 */;
-wire [15:0]raddr /* synthesis syn_keep=1 */;
-wire [15:0]rdata /* synthesis syn_keep=1 */;
-wire re /* synthesis syn_keep=1 */;
+wire clk25m;
+
+wire [15:0]cpu_waddr /* synthesis syn_keep=1 */;
+wire [15:0]cpu_wdata /* synthesis syn_keep=1 */;
+wire cpu_we /* synthesis syn_keep=1 */;
+wire [15:0]cpu_raddr /* synthesis syn_keep=1 */;
+wire [15:0]cpu_rdata /* synthesis syn_keep=1 */;
+wire cpu_re /* synthesis syn_keep=1 */;
+
+reg cpu_reset = 1'b0;
cpu #(
.RWIDTH(16),
.SWIDTH(4)
)cpu0(
- .clk(clk),
- .mem_waddr_o(waddr),
- .mem_wdata_o(wdata),
- .mem_wr_o(we),
- .mem_raddr_o(raddr),
- .mem_rdata_i(rdata),
- .mem_rd_o(re)
+ .clk(clk25m),
+ .mem_waddr_o(cpu_waddr),
+ .mem_wdata_o(cpu_wdata),
+ .mem_wr_o(cpu_we),
+ .mem_raddr_o(cpu_raddr),
+ .mem_rdata_i(cpu_rdata),
+ .mem_rd_o(cpu_re),
+ .reset(cpu_reset)
) /* synthesis syn_keep=1 */;
-assign trace = waddr;
+wire [15:0]dbg_waddr;
+wire [15:0]dbg_wdata;
+wire dbg_we;
+
+spi_debug_ifc sdi(
+ .spi_clk(spi_clk),
+ .spi_cs_i(spi_cs),
+ .spi_data_i(spi_mosi),
+ .spi_data_o(spi_miso),
+ .sys_clk(clk25m),
+ .sys_wr_o(dbg_we),
+ .sys_waddr_o(dbg_waddr),
+ .sys_wdata_o(dbg_wdata)
+ );
+
+// debug interface has priority over cpu writes
+wire we = dbg_we | cpu_we;
+wire [15:0]waddr = dbg_we ? dbg_waddr : cpu_waddr;
+wire [15:0]wdata = dbg_we ? dbg_wdata : cpu_wdata;
+
+wire cs_sram = (waddr[15:12] == 4'h0);
+wire cs_vram = (waddr[15:12] == 4'h8);
+wire cs_ctrl = (waddr[15:12] == 4'hF);
-wire cs0r = ~raddr[8];
+always @(posedge clk25m) begin
+ if (cs_ctrl & we) begin
+ cpu_reset <= wdata[0];
+ end
+end
+
+assign out1 = cpu_reset;
+assign out2 = cpu_raddr[0];
+
+wire cs0r = ~cpu_raddr[8];
+wire cs1r = cpu_raddr[8];
wire cs0w = ~waddr[8];
-wire cs1r = raddr[8];
wire cs1w = waddr[8];
wire [15:0]rdata0;
wire [15:0]rdata1;
-assign rdata = cs0r ? rdata0 : rdata1;
+assign cpu_rdata = cs0r ? rdata0 : rdata1;
sram ram0(
- .clk(clk),
- .raddr(raddr),
+ .clk(clk25m),
+ .raddr(cpu_raddr),
.rdata(rdata0),
- .re(re & cs0r),
+ .re(cpu_re & cs0r & cs_sram),
.waddr(waddr),
.wdata(wdata),
- .we(we & cs0w)
+ .we(we & cs0w & cs_sram)
);
sram ram1(
- .clk(clk),
- .raddr(raddr),
+ .clk(clk25m),
+ .raddr(cpu_raddr),
.rdata(rdata1),
- .re(re & cs0r),
+ .re(re & cs0r & cs_sram),
.waddr(waddr),
.wdata(wdata),
- .we(we & cs0w)
+ .we(we & cs0w & cs_sram)
+ );
+
+pll_12_25 pll0(
+ .REFERENCECLK(clk12m),
+ .PLLOUTGLOBAL(clk25m),
+ .PLLOUTCORE(),
+ .LOCK(),
+ .RESET(1'b1)
+ );
+
+vga40x30x2 vga(
+ .clk25m(clk25m),
+ .red(vga_r),
+ .grn(vga_g),
+ .blu(vga_b),
+ .hs(vga_hsync),
+ .vs(vga_vsync),
+ .vram_waddr(waddr[10:0]),
+ .vram_wdata(wdata[7:0]),
+ .vram_we(we & cs_vram)
);
endmodule
@@ -82,7 +148,8 @@ SB_RAM256x16 sram_inst(
.WDATA(wdata),
.WCLK(clk),
.WCLKE(1'b1),
- .WE(we)
+ .WE(we),
+ .MASK()
);
endmodule
diff --git a/hdl/lattice/pll_12_25.v b/hdl/lattice/pll_12_25.v
@@ -0,0 +1,40 @@
+module pll_12_25(REFERENCECLK,
+ PLLOUTCORE,
+ PLLOUTGLOBAL,
+ RESET,
+ LOCK);
+
+input REFERENCECLK;
+input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
+output PLLOUTCORE;
+output PLLOUTGLOBAL;
+output LOCK;
+
+SB_PLL40_CORE pll_12_25_inst(.REFERENCECLK(REFERENCECLK),
+ .PLLOUTCORE(PLLOUTCORE),
+ .PLLOUTGLOBAL(PLLOUTGLOBAL),
+ .EXTFEEDBACK(),
+ .DYNAMICDELAY(),
+ .RESETB(RESET),
+ .BYPASS(1'b0),
+ .LATCHINPUTVALUE(),
+ .LOCK(LOCK),
+ .SDI(),
+ .SDO(),
+ .SCLK());
+
+//\\ Fin=12, Fout=25;
+defparam pll_12_25_inst.DIVR = 4'b0001;
+defparam pll_12_25_inst.DIVF = 7'b1000010;
+defparam pll_12_25_inst.DIVQ = 3'b100;
+defparam pll_12_25_inst.FILTER_RANGE = 3'b001;
+defparam pll_12_25_inst.FEEDBACK_PATH = "SIMPLE";
+defparam pll_12_25_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
+defparam pll_12_25_inst.FDA_FEEDBACK = 4'b0000;
+defparam pll_12_25_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
+defparam pll_12_25_inst.FDA_RELATIVE = 4'b0000;
+defparam pll_12_25_inst.SHIFTREG_DIV_MODE = 2'b00;
+defparam pll_12_25_inst.PLLOUT_SELECT = "GENCLK";
+defparam pll_12_25_inst.ENABLE_ICEGATE = 1'b0;
+
+endmodule
