gateware

commit eb5ec9b9fcacde2638a58fc8f094a10abae850c2
parent 32342c0526801658f6feeb97fb696c55ceca24cc
Author: Brian Swetland <swetland@frotz.net>
Date:   Thu, 30 Jan 2020 22:30:52 -0800

xorshift: add reset line

Diffstat:
M
hdl/sync_fifo_test.sv
 | 
10
++++++----
M
hdl/xorshift.sv
 | 
8
++++++--

2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/hdl/sync_fifo_test.sv b/hdl/sync_fifo_test.sv
@@ -85,8 +85,9 @@ sync_fifo #(
 // the current value would have been accepted
 xorshift32 xs32wr (
 	.clk(clk),
-	.ready(wr_valid & wr_ready),
-	.data(wr_data)
+	.next(wr_valid & wr_ready),
+	.data(wr_data),
+	.reset(0)
 );
 
 // read verification data stream
@@ -94,8 +95,9 @@ xorshift32 xs32wr (
 // the current value would have been checked
 xorshift32 xs32rd (
 	.clk(clk),
-	.ready(rd_valid & rd_ready),
-	.data(chk_data)
+	.next(rd_valid & rd_ready),
+	.data(chk_data),
+	.reset(0)
 );
 
 endmodule
diff --git a/hdl/xorshift.sv b/hdl/xorshift.sv
@@ -7,7 +7,8 @@ module xorshift32 #(
         parameter INITVAL = 32'hebd5a728
         ) (
         input wire clk,
-        input wire ready,
+        input wire next,
+	input wire reset,
         output reg [31:0]data = INITVAL
 );
 
@@ -19,7 +20,10 @@ wire [31:0] nxt2 = nxt1 ^ { 17'd0, nxt1[31:17] };
 wire [31:0] nxt3 = nxt2 ^ { nxt2[26:0], 5'd0   };
 
 always_ff @(posedge clk)
-        if (ready) data <= nxt3;
+	if (reset)
+		data <= INITVAL;
+	else if (next)
+        	data <= nxt3;
 
 endmodule