commit 57cd05b5497aaf3a5f3438ae945bc90361d6271a
parent f4350c11bb98daae85508b01892fbf5c18e19d48
Author: Brian Swetland <swetland@frotz.net>
Date: Fri, 4 Jul 2014 06:48:53 -0700
zybo-hdmi-axi: overlay a cheesy 60x37 character display over the rgb888 framebuffer
Diffstat:
4 files changed, 1114 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
@@ -17,6 +17,8 @@ MODULE_SRCS += hdl/zynq_ps_1m_1s.sv
MODULE_SRCS += hdl/xilinx_async_fifo.sv hdl/sync_oneway.sv
MODULE_SRCS += hdl/axi_dma_reader.sv
MODULE_SRCS += $(HDMI_SRCS)
+MODULE_SRCS += hdl/chardata8x8.hex
+MODULE_SRCS += hdl/textdisplay.sv
MODULE_SRCS += hdl/zybo_hdmi.xdc
include build/vivado-bitfile.mk
diff --git a/hdl/chardata8x8.hex b/hdl/chardata8x8.hex
@@ -0,0 +1,1024 @@
+00
+00
+00
+00
+00
+00
+00
+00
+00
+3e
+41
+55
+41
+55
+49
+3e
+00
+3e
+7f
+6b
+7f
+6b
+77
+3e
+00
+22
+77
+7f
+7f
+3e
+1c
+08
+00
+08
+1c
+3e
+7f
+3e
+1c
+08
+00
+08
+1c
+2a
+7f
+2a
+08
+1c
+00
+08
+1c
+3e
+7f
+3e
+08
+1c
+00
+00
+1c
+3e
+3e
+3e
+1c
+00
+ff
+ff
+e3
+c1
+c1
+c1
+e3
+ff
+00
+00
+1c
+22
+22
+22
+1c
+00
+ff
+ff
+e3
+dd
+dd
+dd
+e3
+ff
+00
+0f
+03
+05
+39
+48
+48
+30
+00
+08
+3e
+08
+1c
+22
+22
+1c
+00
+18
+14
+10
+10
+30
+70
+60
+00
+0f
+19
+11
+13
+37
+76
+60
+00
+08
+2a
+1c
+77
+1c
+2a
+08
+00
+60
+78
+7e
+7f
+7e
+78
+60
+00
+03
+0f
+3f
+7f
+3f
+0f
+03
+00
+08
+1c
+2a
+08
+2a
+1c
+08
+00
+66
+66
+66
+66
+00
+66
+66
+00
+3f
+65
+65
+3d
+05
+05
+05
+00
+0c
+32
+48
+24
+12
+4c
+30
+00
+00
+00
+00
+00
+7f
+7f
+7f
+00
+08
+1c
+2a
+08
+2a
+1c
+3e
+00
+08
+1c
+3e
+7f
+1c
+1c
+1c
+00
+1c
+1c
+1c
+7f
+3e
+1c
+08
+00
+08
+0c
+7e
+7f
+7e
+0c
+08
+00
+08
+18
+3f
+7f
+3f
+18
+08
+00
+00
+00
+70
+70
+70
+7f
+7f
+00
+00
+14
+22
+7f
+22
+14
+00
+00
+08
+1c
+1c
+3e
+3e
+7f
+7f
+00
+7f
+7f
+3e
+3e
+1c
+1c
+08
+00
+00
+00
+00
+00
+00
+00
+00
+00
+18
+3c
+3c
+18
+18
+00
+18
+00
+36
+36
+14
+00
+00
+00
+00
+00
+36
+36
+7f
+36
+7f
+36
+36
+00
+08
+1e
+20
+1c
+02
+3c
+08
+00
+60
+66
+0c
+18
+30
+66
+06
+00
+3c
+66
+3c
+28
+65
+66
+3f
+00
+18
+18
+18
+30
+00
+00
+00
+00
+60
+30
+18
+18
+18
+30
+60
+00
+06
+0c
+18
+18
+18
+0c
+06
+00
+00
+36
+1c
+7f
+1c
+36
+00
+00
+00
+08
+08
+3e
+08
+08
+00
+00
+00
+00
+00
+30
+30
+30
+60
+00
+00
+00
+00
+3c
+00
+00
+00
+00
+00
+00
+00
+00
+00
+60
+60
+00
+00
+06
+0c
+18
+30
+60
+00
+00
+3c
+66
+6e
+76
+66
+66
+3c
+00
+18
+18
+38
+18
+18
+18
+7e
+00
+3c
+66
+06
+0c
+30
+60
+7e
+00
+3c
+66
+06
+1c
+06
+66
+3c
+00
+0c
+1c
+2c
+4c
+7e
+0c
+0c
+00
+7e
+60
+7c
+06
+06
+66
+3c
+00
+3c
+66
+60
+7c
+66
+66
+3c
+00
+7e
+66
+0c
+0c
+18
+18
+18
+00
+3c
+66
+66
+3c
+66
+66
+3c
+00
+3c
+66
+66
+3e
+06
+66
+3c
+00
+00
+18
+18
+00
+18
+18
+00
+00
+00
+18
+18
+00
+18
+18
+30
+00
+06
+0c
+18
+30
+18
+0c
+06
+00
+00
+00
+3c
+00
+3c
+00
+00
+00
+60
+30
+18
+0c
+18
+30
+60
+00
+3c
+66
+06
+1c
+18
+00
+18
+00
+38
+44
+5c
+58
+42
+3c
+00
+00
+3c
+66
+66
+7e
+66
+66
+66
+00
+7c
+66
+66
+7c
+66
+66
+7c
+00
+3c
+66
+60
+60
+60
+66
+3c
+00
+7c
+66
+66
+66
+66
+66
+7c
+00
+7e
+60
+60
+7c
+60
+60
+7e
+00
+7e
+60
+60
+7c
+60
+60
+60
+00
+3c
+66
+60
+60
+6e
+66
+3c
+00
+66
+66
+66
+7e
+66
+66
+66
+00
+3c
+18
+18
+18
+18
+18
+3c
+00
+1e
+0c
+0c
+0c
+6c
+6c
+38
+00
+66
+6c
+78
+70
+78
+6c
+66
+00
+60
+60
+60
+60
+60
+60
+7e
+00
+63
+77
+7f
+6b
+63
+63
+63
+00
+63
+73
+7b
+6f
+67
+63
+63
+00
+3c
+66
+66
+66
+66
+66
+3c
+00
+7c
+66
+66
+66
+7c
+60
+60
+00
+3c
+66
+66
+66
+6e
+3c
+06
+00
+7c
+66
+66
+7c
+78
+6c
+66
+00
+3c
+66
+60
+3c
+06
+66
+3c
+00
+7e
+5a
+18
+18
+18
+18
+18
+00
+66
+66
+66
+66
+66
+66
+3e
+00
+66
+66
+66
+66
+66
+3c
+18
+00
+63
+63
+63
+6b
+7f
+77
+63
+00
+63
+63
+36
+1c
+36
+63
+63
+00
+66
+66
+66
+3c
+18
+18
+18
+00
+7e
+06
+0c
+18
+30
+60
+7e
+00
+1e
+18
+18
+18
+18
+18
+1e
+00
+00
+60
+30
+18
+0c
+06
+00
+00
+78
+18
+18
+18
+18
+18
+78
+00
+08
+14
+22
+41
+00
+00
+00
+00
+00
+00
+00
+00
+00
+00
+7f
+00
+0c
+0c
+06
+00
+00
+00
+00
+00
+00
+00
+3c
+06
+3e
+66
+3e
+00
+60
+60
+60
+7c
+66
+66
+7c
+00
+00
+00
+3c
+66
+60
+66
+3c
+00
+06
+06
+06
+3e
+66
+66
+3e
+00
+00
+00
+3c
+66
+7e
+60
+3c
+00
+1c
+36
+30
+30
+7c
+30
+30
+00
+00
+3e
+66
+66
+3e
+06
+3c
+00
+60
+60
+60
+7c
+66
+66
+66
+00
+00
+18
+00
+18
+18
+18
+3c
+00
+0c
+00
+0c
+0c
+6c
+6c
+38
+00
+60
+60
+66
+6c
+78
+6c
+66
+00
+18
+18
+18
+18
+18
+18
+18
+00
+00
+00
+63
+77
+7f
+6b
+6b
+00
+00
+00
+7c
+7e
+66
+66
+66
+00
+00
+00
+3c
+66
+66
+66
+3c
+00
+00
+7c
+66
+66
+7c
+60
+60
+00
+00
+3c
+6c
+6c
+3c
+0d
+0f
+00
+00
+00
+7c
+66
+66
+60
+60
+00
+00
+00
+3e
+40
+3c
+02
+7c
+00
+00
+18
+18
+7e
+18
+18
+18
+00
+00
+00
+66
+66
+66
+66
+3e
+00
+00
+00
+00
+66
+66
+3c
+18
+00
+00
+00
+63
+6b
+6b
+6b
+3e
+00
+00
+00
+66
+3c
+18
+3c
+66
+00
+00
+00
+66
+66
+3e
+06
+3c
+00
+00
+00
+3c
+0c
+18
+30
+3c
+00
+0e
+18
+18
+30
+18
+18
+0e
+00
+18
+18
+18
+00
+18
+18
+18
+00
+70
+18
+18
+0c
+18
+18
+70
+00
+00
+00
+3a
+6c
+00
+00
+00
+00
+08
+1c
+36
+63
+41
+41
+7f
diff --git a/hdl/textdisplay.sv b/hdl/textdisplay.sv
@@ -0,0 +1,63 @@
+// Copyright 2014 Brian Swetland <swetland@frotz.net>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`timescale 1ns / 1ps
+
+module textdisplay(
+ input pixclk,
+ input [10:0]xpixel,
+ input [10:0]ypixel,
+ output reg pixel,
+
+ input bufclk,
+ input [11:0]bufaddr,
+ input [7:0]bufdata,
+ input bufwe
+ );
+
+wire [7:0]cdata;
+wire [9:0]caddr;
+
+wire [7:0]bdata;
+wire [11:0]baddr;
+
+assign baddr = { ypixel[9:4], xpixel[9:4] };
+assign caddr = { bdata[6:0], ypixel[3:1] };
+
+always_comb begin
+ case (xpixel[3:1])
+ 0: pixel = cdata[7];
+ 1: pixel = cdata[6];
+ 2: pixel = cdata[5];
+ 3: pixel = cdata[4];
+ 4: pixel = cdata[3];
+ 5: pixel = cdata[2];
+ 6: pixel = cdata[1];
+ 7: pixel = cdata[0];
+ endcase
+end
+
+// text ram
+reg [7:0]buffer[0:4095];
+always @(posedge bufclk)
+ if (bufwe)
+ buffer[bufaddr] <= bufdata;
+assign bdata = buffer[baddr];
+
+// character pattern rom
+reg [7:0]chardata[0:1023];
+initial $readmemh("chardata8x8.hex", chardata);
+assign cdata = chardata[caddr];
+
+endmodule
diff --git a/hdl/zybo_hdmi_axi.sv b/hdl/zybo_hdmi_axi.sv
@@ -124,22 +124,45 @@ axi_dma_reader reader(
reg fifo_reset = 0;
reg [23:0]pattern = 0;
+reg cbufwe = 0;
+reg [11:0]cbufaddr = 0;
+reg [7:0]cbufdata = 0;
+
always_ff @(posedge axiclk) begin
if (wr) begin
case (wreg)
0: fifo_reset <= 1;
1: fb_enable <= wdata[0];
2: pattern <= wdata[23:0];
- default: ;
+ 3: begin
+ cbufwe <= 1;
+ cbufaddr <= wdata[27:16];
+ cbufdata <= wdata[7:0];
+ end
endcase
end else begin
fifo_reset <= 0;
+ cbufwe <= 0;
end
end
+wire text;
+
+textdisplay textdisplay0(
+ .pixclk(pixclk),
+ .xpixel(xpixel),
+ .ypixel(ypixel),
+ .pixel(text),
+ .bufclk(axiclk),
+ .bufaddr(cbufaddr),
+ .bufdata(cbufdata),
+ .bufwe(cbufwe)
+ );
+
wire [23:0]fifo_data;
wire fifo_empty;
-assign {red,grn,blu} = fifo_empty ? pattern : fifo_data;
+
+assign {red,grn,blu} = text ? 24'hffffff : (fifo_empty ? pattern : fifo_data);
xilinx_async_fifo #(.WIDTH(24)) fifo(
.wrclk(axiclk),