commit 9de3d8ddb97b93ef0ee2fd784f86118538f3db13
parent 7e064f67342fb80271521799c7cc6c77e7599e66
Author: Brian Swetland <swetland@frotz.net>
Date: Fri, 25 Jul 2014 20:20:39 -0700
fixup hdl for rmii_rx changes
Diffstat:
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/hdl/test/eth_rmii_test.sv b/hdl/test/eth_rmii_test.sv
@@ -18,8 +18,7 @@
module testbench(input clk);
// RMII transport between tx and rx
-wire eth_d0;
-wire eth_d1;
+wire [1:0]eth_data;
wire eth_en;
@@ -30,11 +29,8 @@ wire txadvance;
eth_rmii_tx tx(
.clk50(clk),
-
- .tx0(eth_d0),
- .tx1(eth_d1),
+ .tx(eth_data),
.txen(eth_en),
-
.data(txdata),
.packet(txpacket),
.busy(txbusy),
@@ -47,12 +43,13 @@ wire rxeop;
eth_rmii_rx rx(
.clk50(clk),
- .rx0(eth_d0),
- .rx1(eth_d1),
+ .rx(eth_data),
.crs_dv(eth_en),
.data(rxdata),
.valid(rxvalid),
- .eop(rxeop)
+ .eop(rxeop),
+ .out_tx(),
+ .out_txen()
);
reg txgo = 0;
diff --git a/hdl/zybo_eth.sv b/hdl/zybo_eth.sv
@@ -59,7 +59,9 @@ eth_rmii_rx phy0rx(
.crs_dv(phy0_crs),
.data(rxdata),
.valid(rxvalid),
- .eop(rxeop)
+ .eop(rxeop),
+ .out_tx(),
+ .out_txen()
);
wire go;