commit f36bd94cb922823b9ae840fa08d1f66800729d8a
parent c4229e71d0034c104deb67700a2fdc6b4b3cec15
Author: Brian Swetland <swetland@frotz.net>
Date: Sun, 27 Jul 2014 23:36:27 -0700
zybo-eth-capture: pass traffic between phy0 and phy1, capture both streams
phy0 -> phy1 4MB capture ring at 0x10000000
phy1 -> phy0 4MB capture ring at 0x10400000
Diffstat:
3 files changed, 167 insertions(+), 19 deletions(-)
diff --git a/Makefile b/Makefile
@@ -79,7 +79,7 @@ include build/vivado-xsim.mk
MODULE_NAME := zybo-eth-capture
MODULE_PART := xc7z010clg400-1
MODULE_SRCS := hdl/zybo_eth_capture.sv
-MODULE_SRCS += hdl/zynq_ps_1m_1s.sv
+MODULE_SRCS += hdl/zynq_ps_1m_2s.sv
MODULE_SRCS += hdl/mmcm_1in_3out.sv
MODULE_SRCS += hdl/eth_capture.sv
MODULE_SRCS += hdl/eth_rmii_rx.sv
@@ -89,7 +89,7 @@ MODULE_SRCS += hdl/sync_oneway.sv
MODULE_SRCS += hdl/axi_ifc.sv
MODULE_SRCS += hdl/axi_dma_writer.sv
MODULE_SRCS += hdl/axi_registers.sv
-MODULE_SRCS += hdl/zybo_eth.xdc
+MODULE_SRCS += hdl/zybo_eth_capture.xdc
include build/vivado-bitfile.mk
MODULE_NAME := zybo-eth
diff --git a/hdl/zybo_eth_capture.sv b/hdl/zybo_eth_capture.sv
@@ -19,12 +19,18 @@ module top(
output [3:0]led,
output phy0_mdc,
- //output phy0_mdio,
output phy0_clk,
output phy0_txen,
output [1:0]phy0_tx,
input phy0_crs,
- input [1:0]phy0_rx
+ input [1:0]phy0_rx,
+
+ output phy1_mdc,
+ output phy1_clk,
+ output phy1_txen,
+ output [1:0]phy1_tx,
+ input phy1_crs,
+ input [1:0]phy1_rx
);
assign led = 0;
@@ -47,53 +53,92 @@ mmcm_1in_3out #(
assign phy0_clk = clk50;
assign phy0_mdc = 1;
+assign phy1_clk = clk50;
+assign phy1_mdc = 1;
-wire [7:0]rxdata;
-wire rxvalid;
-wire rxeop;
-wire rxsop;
+wire [7:0]rx0data;
+wire rx0valid;
+wire rx0eop;
+wire rx0sop;
(* keep_hierarchy = "yes" *)
eth_rmii_rx phy0rx(
.clk50(clk50),
.rx(phy0_rx),
.crs_dv(phy0_crs),
- .data(rxdata),
- .valid(rxvalid),
- .eop(rxeop),
- .sop(rxsop),
- .out_tx(),
- .out_txen()
+ .data(rx0data),
+ .valid(rx0valid),
+ .eop(rx0eop),
+ .sop(rx0sop),
+ .out_tx(phy1_tx),
+ .out_txen(phy1_txen)
+ );
+
+wire [7:0]rx1data;
+wire rx1valid;
+wire rx1eop;
+wire rx1sop;
+
+(* keep_hierarchy = "yes" *)
+eth_rmii_rx phy1rx(
+ .clk50(clk50),
+ .rx(phy1_rx),
+ .crs_dv(phy1_crs),
+ .data(rx1data),
+ .valid(rx1valid),
+ .eop(rx1eop),
+ .sop(rx1sop),
+ .out_tx(phy0_tx),
+ .out_txen(phy0_txen)
);
axi_ifc #(.IWIDTH(12),.AXI3(1)) axi_ctl();
axi_ifc #(.IWIDTH(6),.AXI3(1)) axi_dma0();
+axi_ifc #(.IWIDTH(6),.AXI3(1)) axi_dma1();
zynq_ps7 zynq(
.fclk0(),
.m_axi_gp0_clk(clk),
.m_axi_gp0(axi_ctl),
.s_axi_gp0_clk(clk),
- .s_axi_gp0(axi_dma0)
+ .s_axi_gp0(axi_dma0),
+ .s_axi_gp1_clk(clk),
+ .s_axi_gp1(axi_dma1)
);
reg cap_enable = 0;
reg cap_reset = 0;
+(* keep_hierarchy = "yes" *)
eth_capture #(
.BASE_ADDR(32'h10000000)
) cap0 (
.clk50(clk50),
- .rxsop(rxsop),
- .rxeop(rxeop),
- .rxdata(rxdata),
- .rxvalid(rxvalid),
+ .rxsop(rx0sop),
+ .rxeop(rx0eop),
+ .rxdata(rx0data),
+ .rxvalid(rx0valid),
.clk(clk),
.reset(cap_reset),
.enable(cap_enable),
.axi_dma(axi_dma0)
);
+(* keep_hierarchy = "yes" *)
+eth_capture #(
+ .BASE_ADDR(32'h10400000)
+ ) cap1 (
+ .clk50(clk50),
+ .rxsop(rx1sop),
+ .rxeop(rx1eop),
+ .rxdata(rx1data),
+ .rxvalid(rx1valid),
+ .clk(clk),
+ .reset(cap_reset),
+ .enable(cap_enable),
+ .axi_dma(axi_dma1)
+ );
+
wire wr;
wire [31:0]wdata;
diff --git a/hdl/zybo_eth_capture.xdc b/hdl/zybo_eth_capture.xdc
@@ -0,0 +1,103 @@
+
+##Clock signal
+##IO_L11P_T1_SRCC_35
+set_property PACKAGE_PIN L16 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]
+
+# 30 MHz JTAG TCK
+#create_clock -period 33.333 -name jtag_tck [get_pins log0/port0/bscan/TCK]
+
+# human readable generated clock name
+create_generated_clock -name clk50 [get_pins mmcm0/mmcm_adv_inst/CLKOUT0]
+
+#set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks sys_clk_pin] -group jtag_tck
+
+##LEDs
+##IO_L23P_T3_35
+set_property PACKAGE_PIN M14 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+
+##IO_L23N_T3_35
+set_property PACKAGE_PIN M15 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+
+##IO_0_35
+set_property PACKAGE_PIN G14 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+
+##IO_L3N_T0_DQS_AD1N_35
+set_property PACKAGE_PIN D18 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+
+##Pmod Header JB
+##IO_L15N_T2_DQS_34
+set_property PACKAGE_PIN U20 [get_ports {phy0_rx[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx[1]}]
+
+##IO_L15P_T2_DQS_34
+set_property PACKAGE_PIN T20 [get_ports {phy0_tx[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_tx[0]}]
+set_property SLEW FAST [get_ports {phy0_tx[0]}]
+
+##IO_L16N_T2_34
+set_property PACKAGE_PIN W20 [get_ports {phy0_mdc}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_mdc}]
+
+##IO_L16P_T2_34
+set_property PACKAGE_PIN V20 [get_ports {phy0_crs}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_crs}]
+
+##IO_L17N_T2_34
+set_property PACKAGE_PIN Y19 [get_ports {phy0_rx[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx[0]}]
+
+##IO_L17P_T2_34
+set_property PACKAGE_PIN Y18 [get_ports {phy0_txen}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_txen}]
+set_property SLEW FAST [get_ports {phy0_txen}]
+
+##IO_L22N_T3_34
+set_property PACKAGE_PIN W19 [get_ports {phy0_tx[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_tx[1]}]
+set_property SLEW FAST [get_ports {phy0_tx[1]}]
+
+##IO_L22P_T3_34
+set_property PACKAGE_PIN W18 [get_ports {phy0_clk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_clk}]
+set_property SLEW FAST [get_ports {phy0_clk}]
+set_property DRIVE 8 [get_ports {phy0_clk}]
+
+##Pmod Header JD
+##IO_L5N_T0_34
+set_property PACKAGE_PIN T15 [get_ports {phy1_rx[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy1_rx[1]}]
+
+##IO_L5P_T0_34
+set_property PACKAGE_PIN T14 [get_ports {phy1_tx[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy1_tx[0]}]
+
+##IO_L6N_T0_VREF_34
+set_property PACKAGE_PIN R14 [get_ports {phy1_mdc}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy1_mdc}]
+
+##IO_L6P_T0_34
+set_property PACKAGE_PIN P14 [get_ports {phy1_crs}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy1_crs}]
+
+##IO_L11N_T1_SRCC_34
+set_property PACKAGE_PIN U15 [get_ports {phy1_rx[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy1_rx[0]}]
+
+##IO_L11P_T1_SRCC_34
+set_property PACKAGE_PIN U14 [get_ports {phy1_txen}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy1_txen}]
+
+##IO_L21N_T3_DQS_34
+set_property PACKAGE_PIN V18 [get_ports {phy1_tx[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy1_tx[1]}]
+
+##IO_L21P_T3_DQS_34
+set_property PACKAGE_PIN V17 [get_ports {phy1_clk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy1_clk}]
+
