commit 2516545bbfddc7aa8d588c5ddc9ab726a50a7e60
parent 0ce0f1485385e95fd38d5db6e69d69d6521021a5
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 18 Feb 2012 05:30:01 -0800
de0: add jtag reset/download peripheral and ability, switch to unified memory
Diffstat:
| M | de0/de0board.qsf | | | 4 | +++- |
| M | de0/de0board.v | | | 46 | +++++++++++++++++++++++----------------------- |
| A | de0/jtag.v | | | 181 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | de0/jtagloader.v | | | 73 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
4 files changed, 280 insertions(+), 24 deletions(-)
diff --git a/de0/de0board.qsf b/de0/de0board.qsf
@@ -530,13 +530,15 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
set_global_assignment -name VERILOG_FILE de0board.v
set_global_assignment -name SDC_FILE de0board.sdc
+set_global_assignment -name VERILOG_FILE jtag.v
+set_global_assignment -name VERILOG_FILE jtagloader.v
set_global_assignment -name VERILOG_FILE ../verilog/alu.v
set_global_assignment -name VERILOG_FILE ../verilog/chardata.v
set_global_assignment -name VERILOG_FILE ../verilog/control.v
set_global_assignment -name VERILOG_FILE ../verilog/cpu32.v
+set_global_assignment -name VERILOG_FILE ../verilog/dualsyncram.v
set_global_assignment -name VERILOG_FILE ../verilog/library.v
set_global_assignment -name VERILOG_FILE ../verilog/regfile.v
-set_global_assignment -name VERILOG_FILE ../verilog/syncram.v
set_global_assignment -name VERILOG_FILE ../verilog/vga.v
set_global_assignment -name VERILOG_FILE ../verilog/videoram.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/de0/de0board.v b/de0/de0board.v
@@ -22,7 +22,7 @@ wire [15:0] status;
reg [31:0] count;
assign LEDG = 10'b1111111111;
-assign HEX0_DP = 1'b1;
+assign HEX0_DP = ~reset;
assign HEX1_DP = 1'b1;
assign HEX2_DP = 1'b1;
assign HEX3_DP = 1'b1;
@@ -32,7 +32,7 @@ hex2seven hex1(.in(status[7:4]),.out(HEX1_D));
hex2seven hex2(.in(status[11:8]),.out(HEX2_D));
hex2seven hex3(.in(status[15:12]),.out(HEX3_D));
-wire clk;
+wire clk, reset;
assign clk = CLOCK_50;
reg clk25;
@@ -49,6 +49,9 @@ wire [10:0] vram_addr;
wire [7:0] vram_data;
wire [7:0] line;
+wire [31:0] jtag_addr, jtag_data;
+wire jtag_we;
+
vga vga(
.clk(clk25),
.reset(1'b0),
@@ -89,22 +92,21 @@ videoram #(8,11) vram(
.waddr(d_addr[13:2]),
);
-rom rom(
- .addr(romaddr[9:2]),
- .data(romdata)
- );
-
-syncram #(32,8) ram(
+dualsyncram #(32,12) memory(
.clk(clk),
- .addr(d_addr[9:2]),
- .rdata(d_data_r),
- .wdata(d_data_w),
- .we(d_we && (d_addr[31:10] == 21'b0))
+ .a_addr(jtag_we ? jtag_addr[13:2] : romaddr[13:2]),
+ .a_rdata(romdata),
+ .a_wdata(jtag_data),
+ .a_we(jtag_we),
+ .b_addr(d_addr[13:2]),
+ .b_rdata(d_data_r),
+ .b_wdata(d_data_w),
+ .b_we(d_we && (d_addr[31:14] == 20'd0))
);
cpu32 cpu(
.clk(clk),
- .reset(1'b0),
+ .reset(reset),
.i_addr(romaddr),
.i_data(romdata),
.d_data_r(d_data_r),
@@ -113,6 +115,14 @@ cpu32 cpu(
.d_data_we(d_we)
);
+jtagloader loader(
+ .clk(clk),
+ .addr(jtag_addr),
+ .data(jtag_data),
+ .we(jtag_we),
+ .reset(reset)
+ );
+
endmodule
module hex2seven(
@@ -140,13 +150,3 @@ always @(*) case (in)
endcase
endmodule
-
-module rom(
- input [7:0] addr,
- output [31:0] data
- );
-reg [31:0] rom[0:2**7];
-initial $readmemh("fw.txt", rom);
-assign data = rom[addr];
-endmodule
-
diff --git a/de0/jtag.v b/de0/jtag.v
@@ -0,0 +1,181 @@
+// megafunction wizard: %Virtual JTAG%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: sld_virtual_jtag
+
+// ============================================================
+// File Name: jtag.v
+// Megafunction Name(s):
+// sld_virtual_jtag
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.1 Build 173 11/01/2011 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module jtag (
+ ir_out,
+ tdo,
+ ir_in,
+ tck,
+ tdi,
+ virtual_state_cdr,
+ virtual_state_cir,
+ virtual_state_e1dr,
+ virtual_state_e2dr,
+ virtual_state_pdr,
+ virtual_state_sdr,
+ virtual_state_udr,
+ virtual_state_uir);
+
+ input [3:0] ir_out;
+ input tdo;
+ output [3:0] ir_in;
+ output tck;
+ output tdi;
+ output virtual_state_cdr;
+ output virtual_state_cir;
+ output virtual_state_e1dr;
+ output virtual_state_e2dr;
+ output virtual_state_pdr;
+ output virtual_state_sdr;
+ output virtual_state_udr;
+ output virtual_state_uir;
+
+ wire sub_wire0;
+ wire sub_wire1;
+ wire [3:0] sub_wire2;
+ wire sub_wire3;
+ wire sub_wire4;
+ wire sub_wire5;
+ wire sub_wire6;
+ wire sub_wire7;
+ wire sub_wire8;
+ wire sub_wire9;
+ wire sub_wire10;
+ wire virtual_state_cir = sub_wire0;
+ wire virtual_state_pdr = sub_wire1;
+ wire [3:0] ir_in = sub_wire2[3:0];
+ wire tdi = sub_wire3;
+ wire virtual_state_udr = sub_wire4;
+ wire tck = sub_wire5;
+ wire virtual_state_e1dr = sub_wire6;
+ wire virtual_state_uir = sub_wire7;
+ wire virtual_state_cdr = sub_wire8;
+ wire virtual_state_e2dr = sub_wire9;
+ wire virtual_state_sdr = sub_wire10;
+
+ sld_virtual_jtag sld_virtual_jtag_component (
+ .ir_out (ir_out),
+ .tdo (tdo),
+ .virtual_state_cir (sub_wire0),
+ .virtual_state_pdr (sub_wire1),
+ .ir_in (sub_wire2),
+ .tdi (sub_wire3),
+ .virtual_state_udr (sub_wire4),
+ .tck (sub_wire5),
+ .virtual_state_e1dr (sub_wire6),
+ .virtual_state_uir (sub_wire7),
+ .virtual_state_cdr (sub_wire8),
+ .virtual_state_e2dr (sub_wire9),
+ .virtual_state_sdr (sub_wire10)
+ // synopsys translate_off
+ ,
+ .jtag_state_cdr (),
+ .jtag_state_cir (),
+ .jtag_state_e1dr (),
+ .jtag_state_e1ir (),
+ .jtag_state_e2dr (),
+ .jtag_state_e2ir (),
+ .jtag_state_pdr (),
+ .jtag_state_pir (),
+ .jtag_state_rti (),
+ .jtag_state_sdr (),
+ .jtag_state_sdrs (),
+ .jtag_state_sir (),
+ .jtag_state_sirs (),
+ .jtag_state_tlr (),
+ .jtag_state_udr (),
+ .jtag_state_uir (),
+ .tms ()
+ // synopsys translate_on
+ );
+ defparam
+ sld_virtual_jtag_component.sld_auto_instance_index = "NO",
+ sld_virtual_jtag_component.sld_instance_index = 0,
+ sld_virtual_jtag_component.sld_ir_width = 4,
+ sld_virtual_jtag_component.sld_sim_action = "",
+ sld_virtual_jtag_component.sld_sim_n_scan = 0,
+ sld_virtual_jtag_component.sld_sim_total_length = 0;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: show_jtag_state STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO"
+// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
+// Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: SLD_SIM_ACTION STRING ""
+// Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "0"
+// Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "0"
+// Retrieval info: USED_PORT: ir_in 0 0 4 0 OUTPUT NODEFVAL "ir_in[3..0]"
+// Retrieval info: USED_PORT: ir_out 0 0 4 0 INPUT NODEFVAL "ir_out[3..0]"
+// Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck"
+// Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi"
+// Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo"
+// Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr"
+// Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir"
+// Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr"
+// Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr"
+// Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr"
+// Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr"
+// Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr"
+// Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir"
+// Retrieval info: CONNECT: @ir_out 0 0 4 0 ir_out 0 0 4 0
+// Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0
+// Retrieval info: CONNECT: ir_in 0 0 4 0 @ir_in 0 0 4 0
+// Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0
+// Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0
+// Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL jtag_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/de0/jtagloader.v b/de0/jtagloader.v
@@ -0,0 +1,73 @@
+// Copyright 2012, Brian Swetland
+
+`timescale 1ns/1ns
+
+module jtagloader(
+ input clk,
+ output we,
+ output reg [31:0] addr,
+ output [31:0] data,
+ output reg reset
+ );
+
+parameter IR_CTRL = 4'd0;
+parameter IR_ADDR = 4'd1;
+parameter IR_DATA = 4'd2;
+
+initial reset = 0;
+
+wire update;
+wire [3:0] iir;
+wire tck, tdi, sdr, udr, uir;
+reg [31:0] dr;
+reg [3:0] ir;
+
+jtag jtag0(
+ .tdi(tdi),
+ .tdo(dr[0]),
+ .tck(tck),
+ .ir_in(iir),
+ .virtual_state_sdr(sdr),
+ .virtual_state_udr(udr),
+ .virtual_state_uir(uir)
+ );
+
+always @(posedge tck) begin
+ if (uir) ir <= iir;
+ if (sdr) dr <= { tdi, dr[31:1] };
+ end
+
+sync sync0(
+ .in(udr),
+ .clk_in(tck),
+ .out(update),
+ .clk_out(clk)
+ );
+
+assign data = dr;
+assign we = update & (ir == IR_DATA);
+
+always @(posedge clk)
+ if (update) case (iir)
+ IR_CTRL: reset <= dr[0];
+ IR_ADDR: addr <= dr;
+ IR_DATA: addr <= addr + 32'd4;
+ endcase
+
+endmodule
+
+module sync(
+ input clk_in,
+ input clk_out,
+ input in,
+ output out
+ );
+reg toggle;
+reg [2:0] sync;
+always @(posedge clk_in)
+ if (in) toggle <= ~toggle;
+always @(posedge clk_out)
+ sync <= { sync[1:0], toggle };
+assign out = (sync[2] ^ sync[1]);
+endmodule
+
