cpu32

commit ab4be4238497e8231d507398432f36a968a297b4
parent 2fa71e82ffedabea0088a7f32554139f1f7cf65a
Author: Brian Swetland <swetland@frotz.net>
Date:   Mon,  6 Feb 2012 21:15:04 -0800

cpu: cleanup

- move control logic into control.v
- specify width for constants to avoid confusing quartus

Diffstat:
M
Makefile
 | 
2
+-
M
de0nano/de0nano.qsf
 | 
5
+++++
M
de0nano/de0nano.v
 | 
2
+-
A
verilog/control.v
 | 
39
+++++++++++++++++++++++++++++++++++++++
M
verilog/cpu32.v
 | 
41
+++++++++++++++++++----------------------

5 files changed, 65 insertions(+), 24 deletions(-)
diff --git a/Makefile b/Makefile
@@ -1,7 +1,7 @@
 # Copyright 2012, Brian Swetland.  Use at your own risk.
 
 SRC := verilog/testbench.v
-SRC += verilog/ram.v verilog/rom.v
+SRC += verilog/ram.v verilog/rom.v verilog/control.v
 SRC += verilog/cpu32.v verilog/alu.v verilog/regfile.v
 SRC += verilog/library.v
 
diff --git a/de0nano/de0nano.qsf b/de0nano/de0nano.qsf
@@ -221,6 +221,8 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD OFF
+set_global_assignment -name VERILOG_FILE ../verilog/control.v
 set_global_assignment -name TEXT_FILE fw.txt
 set_global_assignment -name VERILOG_FILE ../verilog/regfile.v
 set_global_assignment -name VERILOG_FILE ../verilog/library.v
@@ -230,4 +232,7 @@ set_global_assignment -name VERILOG_FILE ../verilog/uart.v
 set_global_assignment -name VERILOG_FILE de0nano.v
 set_global_assignment -name VERILOG_FILE aram.v
 set_global_assignment -name SDC_FILE de0nano.sdc
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 \ No newline at end of file
diff --git a/de0nano/de0nano.v b/de0nano/de0nano.v
@@ -37,7 +37,7 @@ assign cs1 = (ramaddr[31:16] == 16'hE000);
 reg [3:0] cntr;
 
 always @(posedge CLOCK_50)
-	cntr <= cntr + 1;
+	cntr <= cntr + 4'b0001;
 	
 //assign clk = CLOCK_50;
 assign clk = cntr[3];
diff --git a/verilog/control.v b/verilog/control.v
@@ -0,0 +1,39 @@
+module control (
+	input [3:0] opcode,
+	input [3:0] opfunc,
+	input ctl_adata_zero,
+	output ctl_regs_we,
+	output ctl_ram_we,
+	output ctl_ram_rd,
+	output ctl_d_or_b,
+	output ctl_branch,
+	output ctl_branch_ind,
+	output ctl_ram_op,
+	output ctl_imm16,
+	output ctl_link_bit,
+	output [3:0] ctl_alu_func
+	);
+
+// cheesy decoder -- TODO: write for real
+assign ctl_regs_we = 
+	(opcode[3:1] == 3'h0) ||
+	(opcode == 4'h2) ||
+	(ctl_branch && ctl_link_bit) ||
+	(ctl_branch_ind && ctl_link_bit);
+assign ctl_d_or_b = ((opcode == 4'h1) || (opcode == 4'h2) || (opcode == 4'h4));
+assign ctl_ram_rd = (opcode == 4'h2);
+assign ctl_ram_we = (opcode == 4'h3);
+assign ctl_ram_op = ((opcode == 4'h2) || (opcode == 4'h3));
+assign ctl_alu_func = ctl_ram_op ? 4'b0010 : opfunc;
+assign ctl_imm16 = (opcode != 4'h0);
+assign ctl_link_bit = opfunc[3]; 
+
+// branch if it is a branch opcode and the condition is met
+// unconditional branches set both condition bits
+assign ctl_branch = (opcode == 4'h4) & 
+	((opfunc[0] & ctl_adata_zero) || (opfunc[1] & (!ctl_adata_zero)));
+assign ctl_branch_ind = (opcode == 4'h5) & 
+	((opfunc[0] & ctl_adata_zero) || (opfunc[1] & (!ctl_adata_zero)));
+
+endmodule
+
diff --git a/verilog/cpu32.v b/verilog/cpu32.v
@@ -36,32 +36,29 @@ wire ctl_branch_ind; // 1 = indirect branch
 wire ctl_link_bit;   // 1 if the link bit is set (only for branches)
 wire ctl_ram_op;
 wire ctl_imm16;      // 0 = bdata, 1 = imm16 -> alu right
-wire ctl_adata_zero;
-
 wire [3:0] ctl_alu_func;
+wire ctl_ram_we;
+wire ctl_ram_rd;
+
+control control(
+	.opcode(opcode),
+	.opfunc(opfunc),
+	.ctl_adata_zero(ctl_adata_zero),
+	.ctl_regs_we(ctl_regs_we),
+	.ctl_d_or_b(ctl_d_or_b),
+	.ctl_branch(ctl_branch),
+	.ctl_branch_ind(ctl_branch_ind),
+	.ctl_ram_op(ctl_ram_op),
+	.ctl_imm16(ctl_imm16),
+	.ctl_ram_we(ctl_ram_we),
+	.ctl_ram_rd(ctl_ram_rd),
+	.ctl_link_bit(ctl_link_bit),
+	.ctl_alu_func(ctl_alu_func)
+	);
 
-// cheesy decoder -- TODO: write for real
-assign ctl_regs_we = 
-	(opcode[3:1] == 0) ||
-	(opcode == 2) ||
-	(ctl_branch && ctl_link_bit) ||
-	(ctl_branch_ind && ctl_link_bit);
-assign ctl_d_or_b = ((opcode == 1) || (opcode == 2) || (opcode == 4));
-assign ctl_ram_rd = (opcode == 2);
-assign ctl_ram_we = (opcode == 3);
-assign ctl_ram_op = ((opcode == 2) || (opcode == 3));
-assign ctl_alu_func = ctl_ram_op ? 4'b0010 : opfunc;
-assign ctl_imm16 = (opcode != 0);
-assign ctl_link_bit = opfunc[3]; 
+wire ctl_adata_zero;
 assign ctl_adata_zero = (adata == 32'h0);
 
-// branch if it is a branch opcode and the condition is met
-// unconditional branches set both condition bits
-assign ctl_branch = (opcode == 4) & 
-	((opfunc[0] & ctl_adata_zero) || (opfunc[1] & (!ctl_adata_zero)));
-assign ctl_branch_ind = (opcode == 5) & 
-	((opfunc[0] & ctl_adata_zero) || (opfunc[1] & (!ctl_adata_zero)));
-
 register #(32) PC (
 	.clk(clk),
 	.en(1),