gateware

commit 074a59a1eb79960b2c35597a1b3baea253e6a97f
parent 667cf5d1b948c4eae5fb951af4530a337d2e8388
Author: Brian Swetland <swetland@frotz.net>
Date:   Wed, 30 Dec 2015 20:40:21 -0800

cleanup, lint fixes, etc

Diffstat:
M
hdl/ice40.sdc
 | 
2
+-
M
hdl/ice40.v
 | 
34
+++++++++++++++++++++++++---------
M
hdl/lattice/pll_12_25.v
 | 
5
+++++
M
hdl/vga/chardata.v
 | 
5
++++-

4 files changed, 35 insertions(+), 11 deletions(-)
diff --git a/hdl/ice40.sdc b/hdl/ice40.sdc
@@ -1,5 +1,5 @@
 
 create_clock -period 83.333 -name {clk12m} [get_ports {clk12m}]
 
-create_clock -period 166.666 -name {x_clk} [get_ports {x_clk}]
+create_clock -period 166.666 -name {spi_clk} [get_ports {spi_clk}]
 
diff --git a/hdl/ice40.v b/hdl/ice40.v
@@ -20,6 +20,8 @@ module top(
 
 wire clk25m;
 
+wire sys_clk = clk12m;
+
 wire [15:0]cpu_waddr /* synthesis syn_keep=1 */;
 wire [15:0]cpu_wdata /* synthesis syn_keep=1 */;
 wire cpu_we /* synthesis syn_keep=1 */;
@@ -33,7 +35,7 @@ cpu #(
 	.RWIDTH(16),
 	.SWIDTH(4)
 	)cpu0(
-	.clk(clk25m),
+	.clk(sys_clk),
 	.mem_waddr_o(cpu_waddr),
 	.mem_wdata_o(cpu_wdata),
 	.mem_wr_o(cpu_we),
@@ -52,7 +54,7 @@ spi_debug_ifc sdi(
 	.spi_cs_i(spi_cs),
 	.spi_data_i(spi_mosi),
 	.spi_data_o(spi_miso),
-	.sys_clk(clk25m),
+	.sys_clk(sys_clk),
 	.sys_wr_o(dbg_we),
 	.sys_waddr_o(dbg_waddr),
 	.sys_wdata_o(dbg_wdata)
@@ -67,14 +69,16 @@ wire cs_sram = (waddr[15:12] == 4'h0);
 wire cs_vram = (waddr[15:12] == 4'h8);
 wire cs_ctrl = (waddr[15:12] == 4'hF);
 
-always @(posedge clk25m) begin
+always @(posedge sys_clk) begin
 	if (cs_ctrl & we) begin
 		cpu_reset <= wdata[0];
 	end
 end
 
-assign out1 = cpu_reset;
-assign out2 = cpu_raddr[0];
+//assign out1 = cpu_reset;
+//assign out2 = cpu_raddr[0];
+assign out1 = cpu_we;
+assign out2 = dbg_we;
 
 wire cs0r = ~cpu_raddr[8];
 wire cs1r = cpu_raddr[8];
@@ -87,7 +91,7 @@ wire [15:0]rdata1;
 assign cpu_rdata = cs0r ? rdata0 : rdata1;
 
 sram ram0(
-	.clk(clk25m),
+	.clk(sys_clk),
 	.raddr(cpu_raddr),
 	.rdata(rdata0),
 	.re(cpu_re & cs0r & cs_sram),
@@ -97,13 +101,13 @@ sram ram0(
 	);
 
 sram ram1(
-	.clk(clk25m),
+	.clk(sys_clk),
 	.raddr(cpu_raddr),
 	.rdata(rdata1),
-	.re(re & cs0r & cs_sram),
+	.re(cpu_re & cs1r & cs_sram),
 	.waddr(waddr),
 	.wdata(wdata),
-	.we(we & cs0w & cs_sram)
+	.we(we & cs1w & cs_sram)
 	);
 
 pll_12_25 pll0(
@@ -138,6 +142,17 @@ module sram(
 	input we
 	);
 
+`ifdef verilator
+reg [15:0]mem[255:0];
+reg [15:0]ra;
+always @(posedge clk) begin
+	if (we)
+		mem[waddr[7:0]] <= wdata;
+	if (re)
+		ra <= raddr;
+	rdata = mem[ra[7:0]];
+end
+`else
 SB_RAM256x16 sram_inst(
 	.RDATA(rdata),
 	.RADDR(raddr[7:0]),
@@ -151,5 +166,6 @@ SB_RAM256x16 sram_inst(
 	.WE(we),
 	.MASK()
 	);
+`endif
 
 endmodule
diff --git a/hdl/lattice/pll_12_25.v b/hdl/lattice/pll_12_25.v
@@ -10,6 +10,10 @@ output PLLOUTCORE;
 output PLLOUTGLOBAL;
 output LOCK;
 
+`ifdef verilator
+assign PLLOUTCORE = REFERENCECLK;
+assign PLLOUTGLOBAL = REFERENCECLK;
+`else
 SB_PLL40_CORE pll_12_25_inst(.REFERENCECLK(REFERENCECLK),
                              .PLLOUTCORE(PLLOUTCORE),
                              .PLLOUTGLOBAL(PLLOUTGLOBAL),
@@ -36,5 +40,6 @@ defparam pll_12_25_inst.FDA_RELATIVE = 4'b0000;
 defparam pll_12_25_inst.SHIFTREG_DIV_MODE = 2'b00;
 defparam pll_12_25_inst.PLLOUT_SELECT = "GENCLK";
 defparam pll_12_25_inst.ENABLE_ICEGATE = 1'b0;
+`endif
 
 endmodule
diff --git a/hdl/vga/chardata.v b/hdl/vga/chardata.v
@@ -128,8 +128,11 @@ always @(*) begin
 	`SLATCH: begin
 		next_state = `SWAIT;
 		next_addr = vram_addr + 11'd1;
-		next_cdata = pattern_rom[{vram_data, pline}];
+		next_cdata = pattern_rom[{vram_data[6:0], pline}];
 		end
+	default: begin
+		next_state = `SWAIT;
+	end
 	endcase
 end