commit 3ae42169ec9e1f04bbbeda3249ea1e11bcb25d10
parent f9491ff9ffcc6cb8a3eb9ea24bd0ced46baf88f1
Author: Brian Swetland <swetland@frotz.net>
Date: Wed, 8 Jan 2020 00:36:27 -0800
cleanup: verilog correctness
- use .sv for files containing systemverilog constructs
- correctly indicate nettypes in module definitions
Diffstat:
12 files changed, 396 insertions(+), 394 deletions(-)
diff --git a/hdl/vga/chardata.sv b/hdl/vga/chardata.sv
@@ -0,0 +1,171 @@
+// Copyright 2018, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+//
+// Character Display Engine
+//
+// newline strobes on the first pixel of a new line
+// advance strobes on each visible pixel of a new line
+// line provides the visible line count 0..239
+//
+// vram_addr/vram_data: connect to sync sram
+
+`default_nettype none
+
+`timescale 1ns/1ns
+
+module pixeldata #(
+ parameter BPP = 2,
+ parameter RGB = 0
+)(
+ input wire clk,
+ input wire newline,
+ input wire advance,
+ input wire [7:0] line,
+ output wire [(3*BPP)-1:0] pixel,
+ input wire [(RGB*8)+7:0] vram_data,
+ output wire [10:0] vram_addr
+);
+
+reg [7:0] pattern_rom [0:1023];
+
+`ifdef HEX_PATHS
+initial $readmemh("hdl/vga/prom.txt", pattern_rom);
+`else
+initial $readmemh("prom.txt", pattern_rom);
+`endif
+
+reg next_load;
+reg next_load_cdata;
+reg next_loaded_cdata;
+reg next_load_pdata;
+reg next_load_pattern;
+reg [5:0] next_xpos;
+reg [3:0] next_ppos;
+reg [15:0] next_pattern;
+
+reg load = 1'b0;
+reg load_cdata = 1'b0;
+reg loaded_cdata = 1'b0;
+reg load_pdata = 1'b0;
+reg load_pattern = 1'b0;
+reg [5:0]xpos = 6'b0;
+reg [3:0]ppos = 4'b0;
+reg [15:0]pattern = 16'b0;
+
+reg [(RGB*8)+7:0]cdata;
+reg [7:0]pdata;
+reg [2:0]fg;
+reg [2:0]bg;
+
+reg set_fg_bg;
+
+wire [(3*BPP)-1:0]FG;
+wire [(3*BPP)-1:0]BG;
+
+if (RGB) begin
+ assign FG = {{BPP{fg[2]}},{BPP{fg[1]}},{BPP{fg[0]}}};
+ assign BG = {{BPP{bg[2]}},{BPP{bg[1]}},{BPP{bg[0]}}};
+end else begin
+ assign FG = { 3*BPP { 1'b1 }};
+ assign BG = { { 2*BPP { 1'b0 }}, { BPP { 1'b1 }} };
+end
+
+// generate vram address by using the high bits of the display
+// line and the local xpos character counter
+assign vram_addr = { line[7:3], xpos };
+
+// generate pattern rom address by using the character id
+// fetched from vram as the high bits and the low bits of
+// the display line to further index into the correct pattern
+wire [9:0] prom_addr = { cdata[6:0], line[2:0] };
+
+`ifdef ASYNC_ROM
+wire [7:0] prom_data = pattern_rom[prom_addr];
+`else
+reg [7:0] prom_data;
+always_ff @(posedge clk)
+ prom_data <= pattern_rom[prom_addr];
+`endif
+
+// double-wide pattern data
+wire [15:0]pdata2x = {
+ pdata[7], pdata[7], pdata[6], pdata[6],
+ pdata[5], pdata[5], pdata[4], pdata[4],
+ pdata[3], pdata[3], pdata[2], pdata[2],
+ pdata[1], pdata[1], pdata[0], pdata[0]
+ };
+
+// the high bit of the pattern shift register is used to
+// select the FG or BG color and feed out to the vga core
+assign pixel = pattern[15] ? FG : BG;
+
+always_comb begin
+ set_fg_bg = 1'b0;
+ next_xpos = xpos;
+ next_ppos = ppos;
+ next_pattern = pattern;
+ next_load = 1'b0;
+
+ // multi-step load (cdata, then pdata, then pattern)
+ next_load_cdata = load;
+ next_loaded_cdata = load_cdata;
+ next_load_pdata = loaded_cdata;
+ next_load_pattern = load_pdata;
+
+ if (newline) begin
+ // reset character counter (xpos), pattern counter (ppos),
+ // and preload the first pattern
+ next_load = 1'b1;
+ next_xpos = 6'b0;
+ next_ppos = 4'b0;
+ end else if (advance) begin
+ next_ppos = ppos + 4'h1;
+ if (ppos == 4'hF) begin
+ // advance to next pattern (preloaded in pdata)
+ next_pattern = pdata2x;
+ set_fg_bg = 1'b1;
+ end else begin
+ // advance to the next bit in the current pattern
+ next_pattern = { pattern[14:0], 1'b0 };
+ if (ppos == 4'd0) begin
+ // advance xpos and start preloading
+ // for the next character
+ next_load = 1'b1;
+ next_xpos = xpos + 6'd1;
+ end
+ end
+ end else begin
+ // handle the final step of preloading the pattern
+ // for xpos 0 (between newline=1 and advance=1)
+ if (load_pattern) begin
+ next_pattern = pdata2x;
+ set_fg_bg = 1'b1;
+ end
+ end
+end
+
+always_ff @(posedge clk) begin
+ load <= next_load;
+ load_cdata <= next_load_cdata;
+ loaded_cdata <= next_loaded_cdata;
+ load_pdata <= next_load_pdata;
+ load_pattern <= next_load_pattern;
+ xpos <= next_xpos;
+ ppos <= next_ppos;
+ pattern <= next_pattern;
+ if (load_cdata)
+ cdata <= vram_data;
+ if (load_pdata)
+ pdata <= prom_data;
+end
+
+if (RGB) begin
+ always_ff @(posedge clk) begin
+ if (set_fg_bg) begin
+ fg <= cdata[14:12];
+ bg <= cdata[10:8];
+ end
+ end
+end
+
+endmodule
diff --git a/hdl/vga/chardata.v b/hdl/vga/chardata.v
@@ -1,171 +0,0 @@
-// Copyright 2018, Brian Swetland <swetland@frotz.net>
-// Licensed under the Apache License, Version 2.0.
-//
-// Character Display Engine
-//
-// newline strobes on the first pixel of a new line
-// advance strobes on each visible pixel of a new line
-// line provides the visible line count 0..239
-//
-// vram_addr/vram_data: connect to sync sram
-
-`default_nettype none
-
-`timescale 1ns/1ns
-
-module pixeldata #(
- parameter BPP = 2,
- parameter RGB = 0
-)(
- input clk,
- input newline,
- input advance,
- input [7:0] line,
- output [(3*BPP)-1:0] pixel,
- input [(RGB*8)+7:0] vram_data,
- output [10:0] vram_addr
-);
-
-reg [7:0] pattern_rom [0:1023];
-
-`ifdef HEX_PATHS
-initial $readmemh("hdl/vga/prom.txt", pattern_rom);
-`else
-initial $readmemh("prom.txt", pattern_rom);
-`endif
-
-reg next_load;
-reg next_load_cdata;
-reg next_loaded_cdata;
-reg next_load_pdata;
-reg next_load_pattern;
-reg [5:0] next_xpos;
-reg [3:0] next_ppos;
-reg [15:0] next_pattern;
-
-reg load = 1'b0;
-reg load_cdata = 1'b0;
-reg loaded_cdata = 1'b0;
-reg load_pdata = 1'b0;
-reg load_pattern = 1'b0;
-reg [5:0]xpos = 6'b0;
-reg [3:0]ppos = 4'b0;
-reg [15:0]pattern = 16'b0;
-
-reg [(RGB*8)+7:0]cdata;
-reg [7:0]pdata;
-reg [2:0]fg;
-reg [2:0]bg;
-
-reg set_fg_bg;
-
-wire [(3*BPP)-1:0]FG;
-wire [(3*BPP)-1:0]BG;
-
-if (RGB) begin
- assign FG = {{BPP{fg[2]}},{BPP{fg[1]}},{BPP{fg[0]}}};
- assign BG = {{BPP{bg[2]}},{BPP{bg[1]}},{BPP{bg[0]}}};
-end else begin
- assign FG = { 3*BPP { 1'b1 }};
- assign BG = { { 2*BPP { 1'b0 }}, { BPP { 1'b1 }} };
-end
-
-// generate vram address by using the high bits of the display
-// line and the local xpos character counter
-assign vram_addr = { line[7:3], xpos };
-
-// generate pattern rom address by using the character id
-// fetched from vram as the high bits and the low bits of
-// the display line to further index into the correct pattern
-wire [9:0] prom_addr = { cdata[6:0], line[2:0] };
-
-`ifdef ASYNC_ROM
-wire [7:0] prom_data = pattern_rom[prom_addr];
-`else
-reg [7:0] prom_data;
-always_ff @(posedge clk)
- prom_data <= pattern_rom[prom_addr];
-`endif
-
-// double-wide pattern data
-wire [15:0]pdata2x = {
- pdata[7], pdata[7], pdata[6], pdata[6],
- pdata[5], pdata[5], pdata[4], pdata[4],
- pdata[3], pdata[3], pdata[2], pdata[2],
- pdata[1], pdata[1], pdata[0], pdata[0]
- };
-
-// the high bit of the pattern shift register is used to
-// select the FG or BG color and feed out to the vga core
-assign pixel = pattern[15] ? FG : BG;
-
-always_comb begin
- set_fg_bg = 1'b0;
- next_xpos = xpos;
- next_ppos = ppos;
- next_pattern = pattern;
- next_load = 1'b0;
-
- // multi-step load (cdata, then pdata, then pattern)
- next_load_cdata = load;
- next_loaded_cdata = load_cdata;
- next_load_pdata = loaded_cdata;
- next_load_pattern = load_pdata;
-
- if (newline) begin
- // reset character counter (xpos), pattern counter (ppos),
- // and preload the first pattern
- next_load = 1'b1;
- next_xpos = 6'b0;
- next_ppos = 4'b0;
- end else if (advance) begin
- next_ppos = ppos + 4'h1;
- if (ppos == 4'hF) begin
- // advance to next pattern (preloaded in pdata)
- next_pattern = pdata2x;
- set_fg_bg = 1'b1;
- end else begin
- // advance to the next bit in the current pattern
- next_pattern = { pattern[14:0], 1'b0 };
- if (ppos == 4'd0) begin
- // advance xpos and start preloading
- // for the next character
- next_load = 1'b1;
- next_xpos = xpos + 6'd1;
- end
- end
- end else begin
- // handle the final step of preloading the pattern
- // for xpos 0 (between newline=1 and advance=1)
- if (load_pattern) begin
- next_pattern = pdata2x;
- set_fg_bg = 1'b1;
- end
- end
-end
-
-always_ff @(posedge clk) begin
- load <= next_load;
- load_cdata <= next_load_cdata;
- loaded_cdata <= next_loaded_cdata;
- load_pdata <= next_load_pdata;
- load_pattern <= next_load_pattern;
- xpos <= next_xpos;
- ppos <= next_ppos;
- pattern <= next_pattern;
- if (load_cdata)
- cdata <= vram_data;
- if (load_pdata)
- pdata <= prom_data;
-end
-
-if (RGB) begin
- always_ff @(posedge clk) begin
- if (set_fg_bg) begin
- fg <= cdata[14:12];
- bg <= cdata[10:8];
- end
- end
-end
-
-endmodule
diff --git a/hdl/vga/vga.sv b/hdl/vga/vga.sv
@@ -0,0 +1,105 @@
+// Copyright 2012, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`default_nettype none
+
+`timescale 1ns/1ns
+
+// Vert: 2xSync 30xBack 480xData 12xFront -> 524 lines
+// Horz: 96xSync 48xBack 640xData 16xFront -> 800 pixels
+//
+// CLK: 25MHz, px=40nS, line=32uS, frame=16.768mS
+
+module vga #(
+ parameter BPP = 4
+)(
+ input wire clk,
+ output wire hs,
+ output wire vs,
+ output wire fr,
+ output wire [BPP-1:0] r,
+ output wire [BPP-1:0] g,
+ output wire [BPP-1:0] b,
+
+ output wire newline,
+ output wire advance,
+ output wire [7:0] line,
+ input wire [(3*BPP)-1:0] pixel
+);
+
+reg hsync = 1'b0;
+reg vsync = 1'b0;
+reg frame = 1'b0;
+reg active = 1'b0;
+reg startline = 1'b0;
+reg [9:0] hcount = 10'b0;
+reg [9:0] vcount = 10'b0;
+
+reg next_hsync;
+reg next_vsync;
+reg next_frame;
+reg next_active;
+reg next_startline;
+reg [9:0] next_hcount;
+reg [9:0] next_vcount;
+
+wire [9:0] adjusted_vcount = next_vcount - 10'd32;
+
+assign hs = hsync;
+assign vs = vsync;
+assign fr = frame;
+assign line = adjusted_vcount[8:1];
+assign advance = active;
+assign newline = startline;
+
+assign r = active ? pixel[(3*BPP)-1:(2*BPP)] : { BPP { 1'b0 }};
+assign g = active ? pixel[(2*BPP)-1:BPP] : { BPP { 1'b0 }};
+assign b = active ? pixel[BPP-1:0] : { BPP { 1'b0 }};
+
+always_comb begin
+ next_hsync = hsync;
+ next_vsync = vsync;
+ next_frame = 1'b0;
+ next_active = 1'b0;
+ next_startline = 1'b0;
+ next_hcount = 10'd0;
+ next_vcount = 10'd0;
+
+ if (hcount == 10'd799) begin
+ if (vcount == 10'd523) begin
+ next_vcount = 10'd0;
+ next_frame = 1'b1;
+ next_vsync = 1'b0;
+ end else
+ next_vcount = vcount + 10'd1;
+ next_hcount = 10'd0;
+ next_hsync = 1'b0;
+ next_startline = 1'b1;
+ end else begin
+ next_vcount = vcount;
+ next_hcount = hcount + 10'd1;
+
+ if (hcount == 10'd96)
+ next_hsync = 1'b1;
+
+ if (vcount == 10'd2)
+ next_vsync = 1'b1;
+
+ if ((vcount > 30) && (vcount < 511))
+ if ((hcount > 142) && (hcount < 783))
+ next_active = 1'b1;
+ end
+
+end
+
+always_ff @(posedge clk) begin
+ hsync <= next_hsync;
+ vsync <= next_vsync;
+ frame <= next_frame;
+ active <= next_active;
+ startline <= next_startline;
+ hcount <= next_hcount;
+ vcount <= next_vcount;
+end
+
+endmodule
diff --git a/hdl/vga/vga.v b/hdl/vga/vga.v
@@ -1,105 +0,0 @@
-// Copyright 2012, Brian Swetland <swetland@frotz.net>
-// Licensed under the Apache License, Version 2.0.
-
-`default_nettype none
-
-`timescale 1ns/1ns
-
-// Vert: 2xSync 30xBack 480xData 12xFront -> 524 lines
-// Horz: 96xSync 48xBack 640xData 16xFront -> 800 pixels
-//
-// CLK: 25MHz, px=40nS, line=32uS, frame=16.768mS
-
-module vga #(
- parameter BPP = 4
-)(
- input clk,
- output hs,
- output vs,
- output fr,
- output [BPP-1:0] r,
- output [BPP-1:0] g,
- output [BPP-1:0] b,
-
- output newline,
- output advance,
- output [7:0] line,
- input [(3*BPP)-1:0] pixel
-);
-
-reg hsync = 1'b0;
-reg vsync = 1'b0;
-reg frame = 1'b0;
-reg active = 1'b0;
-reg startline = 1'b0;
-reg [9:0] hcount = 10'b0;
-reg [9:0] vcount = 10'b0;
-
-reg next_hsync;
-reg next_vsync;
-reg next_frame;
-reg next_active;
-reg next_startline;
-reg [9:0] next_hcount;
-reg [9:0] next_vcount;
-
-wire [9:0] adjusted_vcount = next_vcount - 10'd32;
-
-assign hs = hsync;
-assign vs = vsync;
-assign fr = frame;
-assign line = adjusted_vcount[8:1];
-assign advance = active;
-assign newline = startline;
-
-assign r = active ? pixel[(3*BPP)-1:(2*BPP)] : { BPP { 1'b0 }};
-assign g = active ? pixel[(2*BPP)-1:BPP] : { BPP { 1'b0 }};
-assign b = active ? pixel[BPP-1:0] : { BPP { 1'b0 }};
-
-always_comb begin
- next_hsync = hsync;
- next_vsync = vsync;
- next_frame = 1'b0;
- next_active = 1'b0;
- next_startline = 1'b0;
- next_hcount = 10'd0;
- next_vcount = 10'd0;
-
- if (hcount == 10'd799) begin
- if (vcount == 10'd523) begin
- next_vcount = 10'd0;
- next_frame = 1'b1;
- next_vsync = 1'b0;
- end else
- next_vcount = vcount + 10'd1;
- next_hcount = 10'd0;
- next_hsync = 1'b0;
- next_startline = 1'b1;
- end else begin
- next_vcount = vcount;
- next_hcount = hcount + 10'd1;
-
- if (hcount == 10'd96)
- next_hsync = 1'b1;
-
- if (vcount == 10'd2)
- next_vsync = 1'b1;
-
- if ((vcount > 30) && (vcount < 511))
- if ((hcount > 142) && (hcount < 783))
- next_active = 1'b1;
- end
-
-end
-
-always_ff @(posedge clk) begin
- hsync <= next_hsync;
- vsync <= next_vsync;
- frame <= next_frame;
- active <= next_active;
- startline <= next_startline;
- hcount <= next_hcount;
- vcount <= next_vcount;
-end
-
-endmodule
diff --git a/hdl/vga/vga40x30x2.sv b/hdl/vga/vga40x30x2.sv
@@ -0,0 +1,74 @@
+// Copyright 2012, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`default_nettype none
+
+module vga40x30x2 #(
+ parameter BPP = 2,
+ parameter RGB = 0
+)(
+ input wire clk25m,
+ output wire [BPP-1:0]red,
+ output wire [BPP-1:0]grn,
+ output wire [BPP-1:0]blu,
+ output wire hs,
+ output wire vs,
+ output wire fr,
+ output wire active,
+ input wire vram_clk,
+ input wire [10:0]vram_waddr,
+ input wire [15:0]vram_wdata,
+ input wire vram_we
+);
+
+wire newline;
+wire advance;
+wire [7:0]line;
+wire [(3*BPP)-1:0]pixel;
+
+vga #(
+ .BPP(BPP)
+ ) vga0 (
+ .clk(clk25m),
+ .hs(hs),
+ .vs(vs),
+ .fr(fr),
+ .r(red),
+ .g(grn),
+ .b(blu),
+ .newline(newline),
+ .advance(advance),
+ .line(line),
+ .pixel(pixel)
+ );
+
+assign active = advance;
+
+wire [10:0]vram_raddr;
+wire [(RGB*8)+7:0]vram_rdata;
+
+pixeldata #(
+ .BPP(BPP),
+ .RGB(RGB)
+ ) pixeldata0 (
+ .clk(clk25m),
+ .newline(newline),
+ .advance(advance),
+ .line(line),
+ .pixel(pixel),
+ .vram_data(vram_rdata),
+ .vram_addr(vram_raddr)
+ );
+
+videoram #((RGB*8)+8,11) vram(
+ .rclk(clk25m),
+ .re(1'b1),
+ .rdata(vram_rdata),
+ .raddr(vram_raddr),
+ .wclk(vram_clk),
+ .we(vram_we),
+ .wdata(vram_wdata[(RGB*8)+7:0]),
+ .waddr(vram_waddr[10:0])
+ );
+
+endmodule
diff --git a/hdl/vga/vga40x30x2.v b/hdl/vga/vga40x30x2.v
@@ -1,74 +0,0 @@
-// Copyright 2012, Brian Swetland <swetland@frotz.net>
-// Licensed under the Apache License, Version 2.0.
-
-`default_nettype none
-
-module vga40x30x2 #(
- parameter BPP = 2,
- parameter RGB = 0
-)(
- input clk25m,
- output [BPP-1:0]red,
- output [BPP-1:0]grn,
- output [BPP-1:0]blu,
- output hs,
- output vs,
- output fr,
- output active,
- input vram_clk,
- input [10:0]vram_waddr,
- input [15:0]vram_wdata,
- input vram_we
-);
-
-wire newline;
-wire advance;
-wire [7:0]line;
-wire [(3*BPP)-1:0]pixel;
-
-vga #(
- .BPP(BPP)
- ) vga0 (
- .clk(clk25m),
- .hs(hs),
- .vs(vs),
- .fr(fr),
- .r(red),
- .g(grn),
- .b(blu),
- .newline(newline),
- .advance(advance),
- .line(line),
- .pixel(pixel)
- );
-
-assign active = advance;
-
-wire [10:0]vram_raddr;
-wire [(RGB*8)+7:0]vram_rdata;
-
-pixeldata #(
- .BPP(BPP),
- .RGB(RGB)
- ) pixeldata0 (
- .clk(clk25m),
- .newline(newline),
- .advance(advance),
- .line(line),
- .pixel(pixel),
- .vram_data(vram_rdata),
- .vram_addr(vram_raddr)
- );
-
-videoram #((RGB*8)+8,11) vram(
- .rclk(clk25m),
- .re(1'b1),
- .rdata(vram_rdata),
- .raddr(vram_raddr),
- .wclk(vram_clk),
- .we(vram_we),
- .wdata(vram_wdata[(RGB*8)+7:0]),
- .waddr(vram_waddr[10:0])
- );
-
-endmodule
diff --git a/hdl/vga/videoram.sv b/hdl/vga/videoram.sv
@@ -0,0 +1,42 @@
+// Copyright 2012, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+//
+// sync sram with independent read/write addressing
+
+`default_nettype none
+
+`timescale 1ns/1ns
+
+module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) (
+ input wire wclk,
+ input wire we,
+ input wire [AWIDTH-1:0] waddr,
+ input wire [DWIDTH-1:0] wdata,
+ input wire rclk,
+ input wire re,
+ input wire [AWIDTH-1:0] raddr,
+ output wire [DWIDTH-1:0] rdata
+ );
+
+reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
+reg [DWIDTH-1:0] data;
+
+assign rdata = data;
+
+`ifdef HEX_PATHS
+initial $readmemh("hdl/vga/vram.txt", mem);
+`else
+initial $readmemh("vram.txt", mem);
+`endif
+
+always @(posedge wclk) begin
+ if (we)
+ mem[waddr] <= wdata;
+end
+
+always @(posedge rclk) begin
+ if (re)
+ data <= mem[raddr];
+end
+
+endmodule
diff --git a/hdl/vga/videoram.v b/hdl/vga/videoram.v
@@ -1,40 +0,0 @@
-// Copyright 2012, Brian Swetland <swetland@frotz.net>
-// Licensed under the Apache License, Version 2.0.
-//
-// sync sram with independent read/write addressing
-
-`default_nettype none
-
-`timescale 1ns/1ns
-
-module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) (
- input wclk, input we,
- input [AWIDTH-1:0] waddr,
- input [DWIDTH-1:0] wdata,
- input rclk, input re,
- input [AWIDTH-1:0] raddr,
- output [DWIDTH-1:0] rdata
- );
-
-reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
-reg [DWIDTH-1:0] data;
-
-assign rdata = data;
-
-`ifdef HEX_PATHS
-initial $readmemh("hdl/vga/vram.txt", mem);
-`else
-initial $readmemh("vram.txt", mem);
-`endif
-
-always @(posedge wclk) begin
- if (we)
- mem[waddr] <= wdata;
-end
-
-always @(posedge rclk) begin
- if (re)
- data <= mem[raddr];
-end
-
-endmodule
diff --git a/project/cpu16-icebreaker-hdmi111.def b/project/cpu16-icebreaker-hdmi111.def
@@ -5,7 +5,7 @@ PROJECT_SRCS := hdl/board_icebreaker_hdmi111.v hdl/board_icebreaker_hdmi111.pcf
PROJECT_SRCS += hdl/system_cpu16_vga40x30.v hdl/lattice/pll_12_25.v
#PROJECT_SRCS += hdl/spi_debug_ifc.v
PROJECT_SRCS += hdl/uart_debug_ifc.sv hdl/uart_rx.sv hdl/crc8_serial.sv
-PROJECT_SRCS += hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
+PROJECT_SRCS += hdl/vga/vga40x30x2.sv hdl/vga/vga.sv hdl/vga/videoram.sv hdl/vga/chardata.sv
PROJECT_SRCS += hdl/cpu16.sv hdl/cpu16_regs.sv hdl/cpu16_alu.sv
PROJECT_NEXTPNR_OPTS := --package sg48 --up5k
diff --git a/project/cpu16-icebreaker-vga444.def b/project/cpu16-icebreaker-vga444.def
@@ -5,7 +5,7 @@ PROJECT_SRCS := hdl/board_icebreaker_vga444.v hdl/board_icebreaker_vga444.pcf
PROJECT_SRCS += hdl/system_cpu16_vga40x30.v hdl/lattice/pll_12_25.v
#PROJECT_SRCS += hdl/spi_debug_ifc.v
PROJECT_SRCS += hdl/uart_debug_ifc.sv hdl/uart_rx.sv hdl/crc8_serial.sv
-PROJECT_SRCS += hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
+PROJECT_SRCS += hdl/vga/vga40x30x2.sv hdl/vga/vga.sv hdl/vga/videoram.sv hdl/vga/chardata.sv
PROJECT_SRCS += hdl/cpu16.sv hdl/cpu16_regs.sv hdl/cpu16_alu.sv
PROJECT_NEXTPNR_OPTS := --package sg48 --up5k
diff --git a/project/cpu16-lattice-evb.def b/project/cpu16-lattice-evb.def
@@ -5,7 +5,7 @@ PROJECT_SRCS := hdl/board_lattice_evb.v hdl/board_lattice_evb.pcf
PROJECT_SRCS += hdl/system_cpu16_vga40x30.v hdl/lattice/pll_12_25.v
#PROJECT_SRCS += hdl/spi_debug_ifc.v
PROJECT_SRCS += hdl/uart_debug_ifc.sv hdl/uart_rx.sv hdl/crc8_serial.sv
-PROJECT_SRCS += hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
+PROJECT_SRCS += hdl/vga/vga40x30x2.sv hdl/vga/vga.sv hdl/vga/videoram.sv hdl/vga/chardata.sv
PROJECT_SRCS += hdl/cpu16.sv hdl/cpu16_regs.sv hdl/cpu16_alu.sv
PROJECT_NEXTPNR_OPTS := --package sg48 --up5k
diff --git a/project/vga40x30.def b/project/vga40x30.def
@@ -2,6 +2,6 @@
PROJECT_TYPE := verilator-sim
PROJECT_SRCS := hdl/testvga.sv
-PROJECT_SRCS += hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
+PROJECT_SRCS += hdl/vga/vga40x30x2.sv hdl/vga/vga.sv hdl/vga/videoram.sv hdl/vga/chardata.sv
PROJECT_VOPTS := -CFLAGS -DVGA
