commit 6e25c2cdf5dd79b68bb872156e2fa4f025a46173
parent 3ae42169ec9e1f04bbbeda3249ea1e11bcb25d10
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 11 Jan 2020 03:41:00 -0800
ecp5: build rules and test project for ecp5-evn board
Diffstat:
6 files changed, 216 insertions(+), 0 deletions(-)
diff --git a/build/init.mk b/build/init.mk
@@ -5,8 +5,10 @@
VERILATOR := verilator
NEXTPNR_ICE40 := nextpnr-ice40
+NEXTPNR_ECP5 := nextpnr-ecp5
YOSYS := yosys
ICEPACK := icepack
+ECPPACK := ecppack
ALL_BUILDS :=
ALL_TARGETS :=
diff --git a/build/nextpnr-ecp5.mk b/build/nextpnr-ecp5.mk
@@ -0,0 +1,69 @@
+## Copyright 2020 Brian Swetland <swetland@frotz.net>
+##
+## Licensed under the Apache License, Version 2.0
+## http://www.apache.org/licenses/LICENSE-2.0
+
+PROJECT_OBJDIR := out/-nextpnr-/$(PROJECT_NAME)
+
+PROJECT_CONFIG := $(PROJECT_OBJDIR)/$(PROJECT_NAME)_out.config
+PROJECT_LINT := $(PROJECT_OBJDIR)/$(PROJECT_NAME).lint
+PROJECT_JSON := $(PROJECT_OBJDIR)/$(PROJECT_NAME).json
+PROJECT_YS := $(PROJECT_OBJDIR)/$(PROJECT_NAME).ys
+PROJECT_BIT := out/$(PROJECT_NAME).bit
+PROJECT_SVF := out/$(PROJECT_NAME).svf
+
+PROJECT_VLG_SRCS := $(filter %.v %.sv,$(PROJECT_SRCS))
+PROJECT_LPF_SRCS := $(filter %.lpf,$(PROJECT_SRCS))
+
+$(PROJECT_YS): _SRCS := $(PROJECT_VLG_SRCS)
+$(PROJECT_YS): _JSON := $(PROJECT_JSON)
+$(PROJECT_YS): $(PROJECT_SRCS) $(PROJECT_DEF) build/nextpnr-ecp5.mk
+ @mkdir -p $(dir $@)
+ @echo GENERATING: $@
+ @echo verilog_defines -DHEX_PATHS -DYOSYS > $@
+ @for src in $(_SRCS); do echo read_verilog -sv $$src; done >> $@
+ @echo synth_ecp5 -top top -json $(_JSON) >> $@
+
+$(PROJECT_LINT): _SRCS := $(PROJECT_VLG_SRCS)
+$(PROJECT_LINT): $(PROJECT_SRCS)
+ @mkdir -p $(dir $@)
+ @echo LINTING: $@
+ @$(VERILATOR) --top-module top --lint-only $(_SRCS)
+ @touch $@
+
+$(PROJECT_JSON): _LOG := $(PROJECT_OBJDIR)/$(PROJECT_NAME).yosys.log
+$(PROJECT_JSON): $(PROJECT_YS) $(PROJECT_LINT)
+ @mkdir -p $(dir $@)
+ @echo SYNTHESIZING: $@
+ @$(YOSYS) -s $< 2>&1 | tee $(_LOG)
+
+$(PROJECT_CONFIG): _OPTS := $(PROJECT_NEXTPNR_OPTS)
+$(PROJECT_CONFIG): _LPF := $(foreach lpf,$(PROJECT_LPF_SRCS),--lpf $(lpf))
+$(PROJECT_CONFIG): _LOG := $(PROJECT_OBJDIR)/$(PROJECT_NAME).nextpnr.log
+$(PROJECT_CONFIG): _JSON := $(PROJECT_JSON)
+$(PROJECT_CONFIG): $(PROJECT_JSON) $(PROJECT_LPF_SRCS)
+ @mkdir -p $(dir $@)
+ @echo PLACING-AND-ROUTING: $@
+ $(NEXTPNR_ECP5) --json $(_JSON) --textcfg $@ $(_OPTS) $(_LPF) 2>&1 | tee $(_LOG)
+
+$(PROJECT_BIT): _CONFIG := $(PROJECT_CONFIG)
+$(PROJECT_BIT): _BIT := $(PROJECT_BIT)
+$(PROJECT_BIT): $(PROJECT_CONFIG)
+ @mkdir -p $(dir $@)
+ @echo GENERATING: $@
+ @$(ECPPACK) $(_CONFIG) $(_BIT)
+
+$(PROJECT_SVF): _CONFIG := $(PROJECT_CONFIG)
+$(PROJECT_SVF): _SVF := $(PROJECT_SVF)
+$(PROJECT_SVF): $(PROJECT_CONFIG)
+ @mkdir -p $(dir $@)
+ @echo GENERATING: $@
+ @$(ECPPACK) --svf $(_SVF) $(_CONFIG)
+
+$(PROJECT_NAME): $(PROJECT_BIT)
+
+ALL_TARGETS += $(PROJECT_NAME)
+ALL_BUILDS += $(PROJECT_NAME)
+
+TARGET_$(PROJECT_NAME)_DESC := build ecp5 bitfile: $(PROJECT_BIT)
+
diff --git a/hdl/ecp5_evn_hdmi111.lpf b/hdl/ecp5_evn_hdmi111.lpf
@@ -0,0 +1,40 @@
+LOCATE COMP "clk" SITE "A10";
+IOBUF PORT "clk" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "btn" SITE "P4";
+IOBUF PORT "btn" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "led[0]" SITE "A13";
+LOCATE COMP "led[1]" SITE "A12";
+LOCATE COMP "led[2]" SITE "B19";
+LOCATE COMP "led[3]" SITE "A18";
+LOCATE COMP "led[4]" SITE "B18";
+LOCATE COMP "led[5]" SITE "C17";
+LOCATE COMP "led[6]" SITE "A17";
+LOCATE COMP "led[7]" SITE "B17";
+
+IOBUF PORT "led[0]" IO_TYPE=LVCMOS25;
+IOBUF PORT "led[1]" IO_TYPE=LVCMOS25;
+IOBUF PORT "led[2]" IO_TYPE=LVCMOS25;
+IOBUF PORT "led[3]" IO_TYPE=LVCMOS25;
+IOBUF PORT "led[4]" IO_TYPE=LVCMOS25;
+IOBUF PORT "led[5]" IO_TYPE=LVCMOS25;
+IOBUF PORT "led[6]" IO_TYPE=LVCMOS25;
+IOBUF PORT "led[7]" IO_TYPE=LVCMOS25;
+
+LOCATE COMP "hdmi_g" SITE "C6";
+LOCATE COMP "hdmi_ck" SITE "C7";
+LOCATE COMP "hdmi_hs" SITE "E8";
+LOCATE COMP "hdmi_r" SITE "C8";
+LOCATE COMP "hdmi_b" SITE "B8";
+LOCATE COMP "hdmi_de" SITE "A7";
+LOCATE COMP "hdmi_vs" SITE "A8";
+
+IOBUF PORT "hdmi_g" IO_TYPE=LVCMOS33;
+IOBUF PORT "hdmi_ck" IO_TYPE=LVCMOS33;
+IOBUF PORT "hdmi_hs" IO_TYPE=LVCMOS33;
+IOBUF PORT "hdmi_r" IO_TYPE=LVCMOS33;
+IOBUF PORT "hdmi_b" IO_TYPE=LVCMOS33;
+IOBUF PORT "hdmi_de" IO_TYPE=LVCMOS33;
+IOBUF PORT "hdmi_vs" IO_TYPE=LVCMOS33;
+
diff --git a/hdl/ecp5_evn_hdmi111.sv b/hdl/ecp5_evn_hdmi111.sv
@@ -0,0 +1,43 @@
+module top(
+ input clk,
+ input btn,
+ output [7:0] led,
+ output hdmi_r,
+ output hdmi_g,
+ output hdmi_b,
+ output hdmi_hs,
+ output hdmi_vs,
+ output hdmi_de,
+ output hdmi_ck
+);
+
+ assign led = { 4'b1010, btn, btn, btn, btn };
+
+wire clk25m;
+
+pll_12_25 pll(
+ .clk12m_in(clk),
+ .clk25m_out(clk25m),
+ .locked()
+);
+
+assign hdmi_ck = clk25m;
+
+vga40x30x2 #(
+ .BPP(1),
+ .RGB(0)
+ )hdmi(
+ .clk25m(clk25m),
+ .red(hdmi_r),
+ .grn(hdmi_g),
+ .blu(hdmi_b),
+ .hs(hdmi_hs),
+ .vs(hdmi_vs),
+ .fr(),
+ .active(hdmi_de),
+ .vram_clk(clk25m),
+ .vram_waddr(0),
+ .vram_wdata(0),
+ .vram_we(0)
+ );
+endmodule
diff --git a/hdl/lattice/ecp5_pll_12_25.v b/hdl/lattice/ecp5_pll_12_25.v
@@ -0,0 +1,52 @@
+// $ ecppll -f pll.v -i 12.0 -o 25.0 --clkin_name clk12m_in --clkout0_name clk25m_out
+//
+// diamond 3.7 accepts this PLL
+// diamond 3.8-3.9 is untested
+// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
+// cause of this could be from wrong CPHASE/FPHASE parameters
+module pll_12_25
+(
+ input clk12m_in, // 12 MHz, 0 deg
+ output clk25m_out, // 24 MHz, 0 deg
+ output locked
+);
+
+`ifndef verilator
+(* FREQUENCY_PIN_CLKI="12" *)
+(* FREQUENCY_PIN_CLKOP="24" *)
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+ .PLLRST_ENA("DISABLED"),
+ .INTFB_WAKE("DISABLED"),
+ .STDBY_ENABLE("DISABLED"),
+ .DPHASE_SOURCE("DISABLED"),
+ .OUTDIVIDER_MUXA("DIVA"),
+ .OUTDIVIDER_MUXB("DIVB"),
+ .OUTDIVIDER_MUXC("DIVC"),
+ .OUTDIVIDER_MUXD("DIVD"),
+ .CLKI_DIV(1),
+ .CLKOP_ENABLE("ENABLED"),
+ .CLKOP_DIV(25),
+ .CLKOP_CPHASE(12),
+ .CLKOP_FPHASE(0),
+ .FEEDBK_PATH("CLKOP"),
+ .CLKFB_DIV(2)
+ ) pll_i (
+ .RST(1'b0),
+ .STDBY(1'b0),
+ .CLKI(clk12i),
+ .CLKOP(clk25o),
+ .CLKFB(clk25o),
+ .CLKINTFB(),
+ .PHASESEL0(1'b0),
+ .PHASESEL1(1'b0),
+ .PHASEDIR(1'b1),
+ .PHASESTEP(1'b1),
+ .PHASELOADREG(1'b1),
+ .PLLWAKESYNC(1'b0),
+ .ENCLKOP(1'b0),
+ .LOCK(locked)
+ );
+`endif
+
+endmodule
diff --git a/project/vga40x30-ecp5-evn-hdmi111.def b/project/vga40x30-ecp5-evn-hdmi111.def
@@ -0,0 +1,10 @@
+
+PROJECT_TYPE := nextpnr-ecp5
+
+PROJECT_SRCS := hdl/ecp5_evn_hdmi111.sv hdl/ecp5_evn_hdmi111.lpf
+PROJECT_SRCS += hdl/lattice/ecp5_pll_12_25.v
+#PROJECT_SRCS += hdl/spi_debug_ifc.v
+#PROJECT_SRCS += hdl/uart_debug_ifc.sv hdl/uart_rx.sv hdl/crc8_serial.sv
+PROJECT_SRCS += hdl/vga/vga40x30x2.sv hdl/vga/vga.sv hdl/vga/videoram.sv hdl/vga/chardata.sv
+
+PROJECT_NEXTPNR_OPTS := --um5g-85k --package CABGA381
