gateware

commit 6efc7c530262811ccc35001c4a10310f6b72673f
parent accf776895d300e20209e16c3e5c72c4b3aa66c6
Author: Brian Swetland <swetland@frotz.net>
Date:   Tue,  4 Feb 2020 16:56:45 -0800

sdram: project to synthesize just the sdram

- add synth_{input,output}_wrapper inspired by FPGA Design Elements
- add a wrapper top level module and project for sdram

Diffstat:
A
hdl/sdram/wrapper.sv
 | 
75
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
A
hdl/synth_wrapper.sv
 | 
42
++++++++++++++++++++++++++++++++++++++++++
A
project/synth-sdram-ecp5.def
 | 
10
++++++++++

3 files changed, 127 insertions(+), 0 deletions(-)
diff --git a/hdl/sdram/wrapper.sv b/hdl/sdram/wrapper.sv
@@ -0,0 +1,75 @@
+
+`default_nettype none
+
+module top(
+	input wire clk,
+	input wire a,
+	input wire b,
+	input wire c,
+	output wire d
+);
+
+wire reset;
+wire sdram_clk;
+wire sdram_ras_n;
+wire sdram_cas_n;
+wire sdram_we_n;
+wire [15:0]sdram_data_i;
+wire [15:0]sdram_data_o;
+wire [11:0]sdram_addr;
+wire [19:0]rd_addr;
+wire [3:0]rd_len;
+wire rd_req;
+wire rd_ack;
+wire [15:0]rd_data;
+wire rd_rdy;
+wire [19:0]wr_addr;
+wire [15:0]wr_data;
+wire [3:0]wr_len;
+wire wr_req;
+wire wr_ack;
+
+sdram sdram0(
+	.clk(clk),
+	.reset(reset),
+	.pin_clk(sdram_clk),
+	.pin_ras_n(sdram_ras_n),
+	.pin_cas_n(sdram_cas_n),
+	.pin_we_n(sdram_we_n),
+	.pin_data_i(sdram_data_i),
+	.pin_data_o(sdram_data_o),
+	.pin_addr(sdram_addr),
+	.rd_addr(rd_addr),
+	.rd_len(rd_len),
+	.rd_req(rd_req),
+	.rd_ack(rd_ack),
+	.rd_data(rd_data),
+	.rd_rdy(rd_rdy),
+	.wr_addr(wr_addr),
+	.wr_data(wr_data),
+	.wr_len(wr_len),
+	.wr_req(wr_req),
+	.wr_ack(wr_ack)
+);
+
+synth_input_wrapper #(
+	.WIDTH(83)
+	) wrap_input (
+	.clk(clk),
+	.pin_in(a),
+	.pin_valid(b),
+	.din({ reset, sdram_data_i, rd_addr, rd_len, rd_req,
+		wr_addr, wr_data, wr_len, wr_req })
+);
+
+synth_output_wrapper #(
+	.WIDTH(51)
+	) wrap_output (
+	.clk(clk),
+	.dout( { sdram_clk, sdram_ras_n, sdram_cas_n, sdram_we_n,
+		sdram_data_o, sdram_addr, rd_ack, rd_data, rd_rdy, wr_ack }),
+	.pin_capture(c),
+	.pin_out(d)
+);
+
+endmodule
diff --git a/hdl/synth_wrapper.sv b/hdl/synth_wrapper.sv
@@ -0,0 +1,42 @@
+// Copyright 2020, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+// Inspired by Synthesis Harness Input / Output
+// from Charles LaForest's FPGA Design Elements
+// http://fpgacpu.ca/fpga/index.html
+
+`default_nettype none
+
+module synth_input_wrapper #(
+	parameter WIDTH = 1
+	)(
+	input wire clk,
+	input wire pin_in,
+	input wire pin_valid,
+	(* keep="true" *) output reg [WIDTH-1:0]din = 0
+);
+
+always @(posedge clk)
+	if (pin_valid)
+		din <= { pin_in, din[WIDTH-1:1] };
+
+endmodule
+
+module synth_output_wrapper #(
+	parameter WIDTH = 1
+	)(
+	input wire clk,
+	input wire [WIDTH-1:0]dout,
+	input wire pin_capture,
+	output wire pin_out
+);
+
+(* keep="true" *) reg [WIDTH-1:0]capture;
+
+always @(posedge clk)
+	if (pin_capture)
+		capture <= dout;
+
+assign pin_out = ^capture;
+
+endmodule
diff --git a/project/synth-sdram-ecp5.def b/project/synth-sdram-ecp5.def
@@ -0,0 +1,10 @@
+PROJECT_TYPE := nextpnr-ecp5
+
+PROJECT_SRCS := hdl/sdram/wrapper.sv 
+PROJECT_SRCS += hdl/sdram/sdram.sv
+PROJECT_SRCS += hdl/synth_wrapper.sv
+
+PROJECT_NEXTPNR_OPTS := --25k --package CABGA381 --speed 6 --lpf-allow-unconstrained --freq 133
+
+# bypass the sdram_glue
+PROJECT_VERILOG_DEFS := verilator