commit bdc9a5090407e29bbfab9ca0ec808158438073d3
parent 420f5dc6dff686a397c108bb67538b9e8d40e56b
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 8 Dec 2018 11:29:50 -0800
build: overhaul the build system
- new build system is driven by project/*.def and makes it easy to
add additional bitfile or simulation projects
- default build target is now to list all build targets
- commandline tools and cpu16 tests are not yet project driven
Diffstat:
8 files changed, 184 insertions(+), 82 deletions(-)
diff --git a/Makefile b/Makefile
@@ -1,86 +1,34 @@
+## Copyright 2018 Brian Swetland <swetland@frotz.net>
+##
+## Licensed under the Apache License, Version 2.0
+## http://www.apache.org/licenses/LICENSE-2.0
-#CPU_SRCS := hdl/cpu/cpu.v hdl/cpu/alu.v hdl/cpu/regfile.v
-CPU_SRCS := hdl/cpu16.sv hdl/cpu16_regs.sv hdl/cpu16_alu.sv
-VGA_SRCS := hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
+#### Projects ####
-VSIM_CPU_SRCS := hdl/testbench.sv hdl/simram.sv $(CPU_SRCS)
+include build/init.mk
-VSIM_VGA_SRCS := hdl/testvga.sv $(VGA_SRCS)
+help: list-all-targets
-ICE40_SRCS := hdl/ice40.v hdl/spi_debug_ifc.v hdl/lattice/pll_12_25.v
-ICE40_SRCS += $(CPU_SRCS) $(VGA_SRCS)
+all: build-all-buildable
-USE_NEXTPNR ?= true
+$(foreach p,$(wildcard project/*.def),$(call project,$p))
-VERILATOR := verilator
-ARACHNEPNR := arachne-pnr
-NEXTPNR := nextpnr-ice40
-YOSYS := yosys
-ICEPACK := icepack
+clean::
+ rm -rf out
-VOPTS_CPU := --top-module testbench --Mdir out/cpu
-VOPTS_CPU += --exe ../src/testbench.cpp --cc -CFLAGS -DTRACE --trace
+ALL_TARGETS := $(sort $(ALL_TARGETS)) tools cpu16-tests all
+TARGET_all_DESC := build all 'build' targets
+TARGET_tools_DESC := build tools: out/{a16,d16,icetool}
+TARGET_cpu16-tests_DESC := run cpu16 test suite
-VOPTS_VGA := --top-module testbench --Mdir out/vga
-VOPTS_VGA += --exe ../src/testbench.cpp --cc -CFLAGS -DTRACE -CFLAGS -DVGA --trace
+list-all-targets::
+ @true
+ $(info All Possible Targets)
+ $(info --------------------)
+ $(foreach x,$(ALL_TARGETS),$(info $(shell printf "%-25s %s\n" "$(x)" "$(TARGET_$(x)_DESC)")))
-all: out/cpu/Vtestbench out/ice40.bin out/a16 out/d16 out/icetool
-
-vga: out/vga/Vtestbench
-
-out/cpu/Vtestbench: $(VSIM_CPU_SRCS) src/testbench.cpp
- @mkdir -p out/cpu
- @$(VERILATOR) $(VOPTS_CPU) $(VSIM_CPU_SRCS)
- @make -C out/cpu -f Vtestbench.mk
-
-out/vga/Vtestbench: $(VSIM_VGA_SRCS) src/testbench.cpp
- @mkdir -p out/vga
- @$(VERILATOR) $(VOPTS_VGA) $(VSIM_VGA_SRCS)
- @make -C out/vga -f Vtestbench.mk
-
-out/ice40.bin: out/ice40.asc
- @mkdir -p out
- $(ICEPACK) $< $@
-
-out/ice40.lint: $(ICE40_SRCS)
- @mkdir -p out
- $(VERILATOR) --top-module top --lint-only $(ICE40_SRCS)
- @touch out/ice40.lint
-
-out/ice40.ys: $(ICE40_SRCS) Makefile
- @mkdir -p out
- @echo generating $@
- @echo verilog_defines -DHEX_PATHS -DYOSYS > $@
- @for src in $(ICE40_SRCS) ; do echo read_verilog -sv $$src ; done >> $@
- @echo synth_ice40 -top top -blif out/ice40.blif -json out/ice40.json >> $@
-
-ifeq ($(USE_NEXTPNR), true)
-out/ice40.json: out/ice40.ys out/ice40.lint
- @mkdir -p out
- $(YOSYS) -s out/ice40.ys 2>&1 | tee out/ice40.synth.log
-
-out/ice40.asc: out/ice40.json
- @mkdir -p out
- $(NEXTPNR) --package sg48 --up5k --pcf hdl/ice40up.pcf --asc out/ice40.asc --json out/ice40.json 2>&1 | tee out/ice40.pnr.log
-else
-out/ice40.blif: out/ice40.ys out/ice40.lint
- @mkdir -p out
- $(YOSYS) -s out/ice40.ys 2>&1 | tee out/ice40.synth.log
-
-out/ice40.asc: out/ice40.blif
- @mkdir -p out
- $(ARACHNEPNR) -d 5k -p sg48 -o out/ice40.asc -p hdl/ice40up.pcf out/ice40.blif 2>&1 | tee out/ice40.pnr.log
-endif
-
-run: out/cpu/Vtestbench out/test16.hex
- ./out/cpu/Vtestbench -trace out/trace.vcd -dump out/memory.bin -load out/test16.hex
-
-out/test16.hex: src/test16.s out/a16 out/d16
- out/a16 src/test16.s out/test16.hex
-
-#out/test.hex: test.hex
-# cp test.hex out/test.hex
+#### Tools ####
out/a16: src/a16v5.c src/d16v5.c
@mkdir -p out
@@ -94,20 +42,24 @@ out/icetool: src/icetool.c src/ftdi.c src/ftdi.h
@mkdir -p out
gcc -g -Wall -O1 -o out/icetool src/icetool.c src/ftdi.c -lusb-1.0 -lrt
-TEST_DEPS := out/cpu/Vtestbench out/a16 out/d16 tests/runtest
+tools:: out/a16 out/d16 out/icetool
+
+build-all-buildable:: $(ALL_BUILDS) tools
+
-TESTS := $(sort $(wildcard tests/*.s))
+#### CPU16 TESTS ####
-RESULTS := $(patsubst %.s,out/%.s.status,$(TESTS))
+CPU16_TEST_DEPS := out/cpu16-vsim out/a16 out/d16 tests/runtest
-out/tests/%.s.status: tests/%.s $(TEST_DEPS)
+CPU16_TESTS := $(sort $(wildcard tests/*.s))
+
+CPU16_RESULTS := $(patsubst %.s,out/%.s.status,$(CPU16_TESTS))
+
+out/tests/%.s.status: tests/%.s $(CPU16_TEST_DEPS)
@./tests/runtest $<
-test: $(RESULTS)
+cpu16-tests: $(CPU16_RESULTS)
@echo ""
@echo TESTS FAILED: `grep FAIL out/tests/*.status | wc -l`
@echo TESTS PASSED: `grep PASS out/tests/*.status | wc -l`
-clean:
- rm -rf out/
-
diff --git a/build/init.mk b/build/init.mk
@@ -0,0 +1,26 @@
+## Copyright 2018 Brian Swetland <swetland@frotz.net>
+##
+## Licensed under the Apache License, Version 2.0
+## http://www.apache.org/licenses/LICENSE-2.0
+
+VERILATOR := verilator
+NEXTPNR_ICE40 := nextpnr-ice40
+YOSYS := yosys
+ICEPACK := icepack
+
+ALL_BUILDS :=
+ALL_TARGETS :=
+
+define project
+$(eval PROJECT_DEF := $1)\
+$(eval PROJECT_TYPE :=)\
+$(eval PROJECT_SRCS :=)\
+$(eval PROJECT_VOPTS :=)\
+$(eval PROJECT_NEXTPNR_OPTS :=)\
+$(eval include $(PROJECT_DEF))\
+$(eval PROJECT_NAME := $(patsubst project/%.def,%,$(PROJECT_DEF)))\
+$(eval pr-inc := $(wildcard $(patsubst %,build/%.mk,$(PROJECT_TYPE))))\
+$(if $(pr-inc),,$(error $1: unknown project type: "$(PROJECT_TYPE)"))\
+$(eval include $(pr-inc))
+endef
+
diff --git a/build/nextpnr-ice40.mk b/build/nextpnr-ice40.mk
@@ -0,0 +1,58 @@
+## Copyright 2018 Brian Swetland <swetland@frotz.net>
+##
+## Licensed under the Apache License, Version 2.0
+## http://www.apache.org/licenses/LICENSE-2.0
+
+PROJECT_OBJDIR := out/-nextpnr-/$(PROJECT_NAME)
+
+PROJECT_BIN := out/$(PROJECT_NAME).bin
+PROJECT_ASC := $(PROJECT_OBJDIR)/$(PROJECT_NAME).asc
+PROJECT_LINT := $(PROJECT_OBJDIR)/$(PROJECT_NAME).lint
+PROJECT_JSON := $(PROJECT_OBJDIR)/$(PROJECT_NAME).json
+PROJECT_YS := $(PROJECT_OBJDIR)/$(PROJECT_NAME).ys
+
+PROJECT_VLG_SRCS := $(filter %.v %.sv,$(PROJECT_SRCS))
+PROJECT_PCF_SRCS := $(filter %.pcf,$(PROJECT_SRCS))
+
+$(PROJECT_YS): _SRCS := $(PROJECT_VLG_SRCS)
+$(PROJECT_YS): _JSON := $(PROJECT_JSON)
+$(PROJECT_YS): $(PROJECT_SRCS) $(PROJECT_DEF) build/nextpnr-ice40.mk
+ @mkdir -p $(dir $@)
+ @echo GENERATING: $@
+ @echo verilog_defines -DHEX_PATHS -DYOSYS > $@
+ @for src in $(_SRCS); do echo read_verilog -sv $$src; done >> $@
+ @echo synth_ice40 -top top -json $(_JSON) >> $@
+
+$(PROJECT_LINT): _SRCS := $(PROJECT_VLG_SRCS)
+$(PROJECT_LINT): $(PROJECT_SRCS)
+ @mkdir -p $(dir $@)
+ @echo LINTING: $@
+ @$(VERILATOR) --top-module top --lint-only $(_SRCS)
+ @touch $@
+
+$(PROJECT_JSON): _LOG := $(PROJECT_OBJDIR)/$(PROJECT_NAME).yosys.log
+$(PROJECT_JSON): $(PROJECT_YS) $(PROJECT_LINT)
+ @mkdir -p $(dir $@)
+ @echo SYNTHESIZING: $@
+ @$(YOSYS) -s $< 2>&1 | tee $(_LOG)
+
+$(PROJECT_ASC): _OPTS := $(PROJECT_NEXTPNR_OPTS)
+$(PROJECT_ASC): _PCF := $(foreach pcf,$(PROJECT_PCF_SRCS),--pcf $(pcf))
+$(PROJECT_ASC): _LOG := $(PROJECT_OBJDIR)/$(PROJECT_NAME).nextpnr.log
+$(PROJECT_ASC): $(PROJECT_JSON) $(PROJECT_PCF_SRCS)
+ @mkdir -p $(dir $@)
+ @echo PLACING-AND-ROUTING: $@
+ @$(NEXTPNR_ICE40) --asc $@ --json $< $(_PCF) $(_OPTS) 2>&1 | tee $(_LOG)
+
+$(PROJECT_BIN): $(PROJECT_ASC)
+ @mkdir -p $(dir $@)
+ @echo PACKING: $@
+ @$(ICEPACK) $< $@
+
+$(PROJECT_NAME): $(PROJECT_BIN)
+
+ALL_TARGETS += $(PROJECT_NAME)
+ALL_BUILDS += $(PROJECT_NAME)
+
+TARGET_$(PROJECT_NAME)_DESC := build ice40 bitfile: $(PROJECT_BIN)
+
diff --git a/build/verilator-sim.mk b/build/verilator-sim.mk
@@ -0,0 +1,44 @@
+## Copyright 2018 Brian Swetland <swetland@frotz.net>
+##
+## Licensed under the Apache License, Version 2.0
+## http://www.apache.org/licenses/LICENSE-2.0
+
+PROJECT_OBJDIR := out/-vsim-/$(PROJECT_NAME)
+PROJECT_RUN := $(PROJECT_NAME)-vsim
+PROJECT_BIN := out/$(PROJECT_NAME)-vsim
+
+PROJECT_VLG_SRCS := $(filter %.v %.sv,$(PROJECT_SRCS))
+
+PROJECT_OPTS := --top-module testbench
+PROJECT_OPTS += --Mdir $(PROJECT_OBJDIR)
+PROJECT_OPTS += --exe ../../src/testbench.cpp
+PROJECT_OPTS += --cc
+PROJECT_OPTS += -o ../../$(PROJECT_NAME)-vsim
+PROJECT_OPTS += -DSIMULATION
+PROJECT_OPTS += $(PROJECT_VOPTS)
+
+PROJECT_OPTS += -CFLAGS -DTRACE --trace
+
+$(PROJECT_BIN): _NAME := $(PROJECT_NAME)
+$(PROJECT_BIN): _SRCS := $(PROJECT_VLG_SRCS)
+$(PROJECT_BIN): _OPTS := $(PROJECT_OPTS)
+$(PROJECT_BIN): _DIR := $(PROJECT_OBJDIR)
+
+$(PROJECT_BIN): $(PROJECT_SRCS) $(PROJECT_DEF)
+ @mkdir -p $(_DIR) bin
+ @echo "COMPILE (verilator): $(_NAME)"
+ @$(VERILATOR) $(_OPTS) $(_SRCS)
+ @echo "COMPILE (C++): $(_NAME)"
+ make -C $(_DIR) -f Vtestbench.mk
+
+$(PROJECT_NAME): $(PROJECT_BIN)
+
+$(PROJECT_RUN): $(PROJECT_BIN)
+ @$<
+
+ALL_TARGETS += $(PROJECT_NAME) $(PROJECT_RUN)
+ALL_BUILDS += $(PROJECT_NAME)
+
+TARGET_$(PROJECT_NAME)_DESC := build verilator sim: $(PROJECT_BIN)
+TARGET_$(PROJECT_RUN)_DESC := run verilator sim: $(PROJECT_BIN)
+
diff --git a/project/cpu16-lattice-evb.def b/project/cpu16-lattice-evb.def
@@ -0,0 +1,10 @@
+
+PROJECT_TYPE := nextpnr-ice40
+
+PROJECT_SRCS := hdl/ice40.v hdl/lattice/pll_12_25.v
+PROJECT_SRCS += hdl/spi_debug_ifc.v
+PROJECT_SRCS += hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
+PROJECT_SRCS += hdl/cpu16.sv hdl/cpu16_regs.sv hdl/cpu16_alu.sv
+PROJECT_SRCS += hdl/ice40up.pcf
+
+PROJECT_NEXTPNR_OPTS := --package sg48 --up5k
diff --git a/project/cpu16.def b/project/cpu16.def
@@ -0,0 +1,5 @@
+
+PROJECT_TYPE := verilator-sim
+
+PROJECT_SRCS := hdl/testbench.sv hdl/simram.sv
+PROJECT_SRCS += hdl/cpu16.sv hdl/cpu16_regs.sv hdl/cpu16_alu.sv
diff --git a/project/vga40x30.def b/project/vga40x30.def
@@ -0,0 +1,7 @@
+
+PROJECT_TYPE := verilator-sim
+
+PROJECT_SRCS := hdl/testvga.sv
+PROJECT_SRCS += hdl/vga/vga40x30x2.v hdl/vga/vga.v hdl/vga/videoram.v hdl/vga/chardata.v
+
+PROJECT_VOPTS := -CFLAGS -DVGA
diff --git a/tests/runtest b/tests/runtest
@@ -17,7 +17,7 @@ if ! ./out/a16 "$1" "out/$1.hex" ; then
exit 0
fi
-if ! ./out/cpu/Vtestbench -trace "out/$1.vcd" -load "out/$1.hex" > "out/$1.raw" ; then
+if ! ./out/cpu16-vsim -trace "out/$1.vcd" -load "out/$1.hex" > "out/$1.raw" ; then
echo FAIL: Error simulating $1
echo FAIL > "out/$1.status"
exit 0
