commit 527a60a15a47846538e2f0532a1941877c9c2ab0
parent cd483ab2e8cb26090e5c77c3ad418e46b93ed610
Author: Brian Swetland <swetland@frotz.net>
Date: Mon, 21 Jul 2014 01:42:41 -0700
ethernet stuff
- use [1:0]tx/rx instead of tx0/tx1 etc
- rearrange zybo-eth pin mappings
- add the tx block to zybo-eth and allow a test packet to be sent
Diffstat:
6 files changed, 147 insertions(+), 50 deletions(-)
diff --git a/Makefile b/Makefile
@@ -60,9 +60,11 @@ MODULE_NAME := zybo-eth
MODULE_PART := xc7z010clg400-1
MODULE_SRCS := hdl/zybo_eth.sv
MODULE_SRCS += hdl/eth_rmii_rx.sv
+MODULE_SRCS += hdl/eth_rmii_tx.sv
MODULE_SRCS += hdl/mmcm_1in_3out.sv
MODULE_SRCS += hdl/jtag_debug_port.sv
MODULE_SRCS += hdl/zybo_eth.xdc
+MODULE_SRCS += hdl/testpacket.hex
include build/vivado-bitfile.mk
clean::
diff --git a/hdl/eth_rmii_rx.sv b/hdl/eth_rmii_rx.sv
@@ -30,8 +30,7 @@
module eth_rmii_rx(
input clk50,
- input rx0,
- input rx1,
+ input [1:0]rx,
input crs_dv,
output reg [7:0]data = 0,
@@ -52,9 +51,7 @@ reg [7:0]next_data;
reg next_valid;
reg next_eop;
-wire [7:0]rxshift = { rx1, rx0, data[7:2] };
-
-wire [1:0]rxd = { rx1, rx0 };
+wire [7:0]rxshift = { rx, data[7:2] };
always_comb begin
next_state = state;
@@ -63,24 +60,24 @@ always_comb begin
next_eop = 0;
case (state)
- IDLE: if ((rxd == 2'b01) && (crs_dv == 1)) begin
+ IDLE: if ((rx == 2'b01) && (crs_dv == 1)) begin
// crs_dv may go high asynchronously
// only move to preamble on crs_dv AND a preamble di-bit
next_state = PRE1;
end
- PRE1: if (rxd == 2'b01) begin
+ PRE1: if (rx == 2'b01) begin
next_state = PRE2;
end else begin
next_state = ERR0;
end
- PRE2: if (rxd == 2'b01) begin
+ PRE2: if (rx == 2'b01) begin
next_state = PRE3;
end else begin
next_state = ERR0;
end
- PRE3: if (rxd == 2'b11) begin
+ PRE3: if (rx == 2'b11) begin
next_state = DAT0;
- end else if (rxd == 2'b01) begin
+ end else if (rx == 2'b01) begin
next_state = PRE3;
end else begin
next_state = ERR0;
diff --git a/hdl/eth_rmii_tx.sv b/hdl/eth_rmii_tx.sv
@@ -24,8 +24,7 @@
module eth_rmii_tx(
input clk50,
- output tx0,
- output tx1,
+ output reg [1:0]tx = 0,
output reg txen = 0,
input [7:0]data,
@@ -46,10 +45,6 @@ reg [7:0] next_txdata;
wire [7:0]txshift = { 2'b0, txdata[7:2] };
-reg [1:0]txd = 0;
-reg [1:0]next_txd;
-
-assign { tx1, tx0 } = txd;
reg [5:0] count = 0;
reg [5:0] next_count;
@@ -59,6 +54,7 @@ wire count_is_zero = (count == 0);
wire [5:0]count_minus_one = (count - 1);
reg next_txen;
+reg [1:0]next_tx;
reg next_advance;
reg next_busy;
@@ -67,14 +63,14 @@ always_comb begin
next_count = count;
next_txdata = txdata;
next_busy = busy;
- next_txd = txd;
+ next_tx = tx;
next_txen = 1;
next_advance = 0;
case (state)
IDLE: begin
next_txen = 0;
- next_txd = 0;
+ next_tx = 0;
if (packet) begin
next_state = PRE;
next_count = 31;
@@ -86,29 +82,29 @@ always_comb begin
next_state = DAT0;
next_txdata = data;
next_advance = 1;
- next_txd = 2'b11;
+ next_tx = 2'b11;
end else begin
- next_txd = 2'b01;
+ next_tx = 2'b01;
next_count = count_minus_one;
end
end
DAT0: begin
next_state = DAT1;
next_txdata = txshift;
- next_txd = txdata[1:0];
+ next_tx = txdata[1:0];
end
DAT1: begin
next_state = DAT2;
next_txdata = txshift;
- next_txd = txdata[1:0];
+ next_tx = txdata[1:0];
end
DAT2: begin
next_state = DAT3;
next_txdata = txshift;
- next_txd = txdata[1:0];
+ next_tx = txdata[1:0];
end
DAT3: begin
- next_txd = txdata[1:0];
+ next_tx = txdata[1:0];
if (~packet) begin
// no more data, wrap it up
next_state = EOP;
@@ -120,7 +116,7 @@ always_comb begin
end
end
EOP: begin
- next_txd = 0;
+ next_tx = 0;
next_txen = 0;
if (count_is_zero) begin
next_state = IDLE;
@@ -137,7 +133,7 @@ always_ff @(posedge clk50) begin
count <= next_count;
txdata <= next_txdata;
txen <= next_txen;
- txd <= next_txd;
+ tx <= next_tx;
advance <= next_advance;
busy <= next_busy;
end
diff --git a/hdl/testpacket.hex b/hdl/testpacket.hex
@@ -0,0 +1,64 @@
+ff
+ff
+ff
+ff
+ff
+ff
+00
+10
+20
+30
+40
+50
+ee
+ee
+00
+01
+02
+03
+04
+05
+06
+07
+08
+09
+0a
+0b
+0c
+0d
+0e
+0f
+00
+00
+55
+55
+55
+55
+aa
+aa
+aa
+aa
+10
+20
+30
+40
+11
+22
+33
+44
+f1
+f2
+f3
+f4
+1f
+2f
+3f
+4f
+de
+ad
+be
+ef
+72
+7c
+4f
+65
diff --git a/hdl/zybo_eth.sv b/hdl/zybo_eth.sv
@@ -18,14 +18,13 @@ module top(
input clk,
output [3:0]led,
+ output phy0_mdc,
+ //output phy0_mdio,
output phy0_clk,
output phy0_txen,
- output phy0_tx0,
- output phy0_mdc,
- output phy0_mdio,
+ output [1:0]phy0_tx,
input phy0_crs,
- input phy0_rx0,
- input phy0_rx1
+ input [1:0]phy0_rx
);
assign led = 0;
@@ -48,31 +47,63 @@ mmcm_1in_3out #(
assign phy0_clk = clk50;
assign phy0_mdc = 1;
-assign phy0_mdio = 0;
-assign phy0_tx0 = 0;
-assign phy0_txen = 0;
wire [7:0]rxdata;
wire rxvalid;
wire rxeop;
(* keep_hierarchy = "yes" *)
-eth_rmii_rx phy0(
+eth_rmii_rx phy0rx(
.clk50(clk50),
- .rx0(phy0_rx0),
- .rx1(phy0_rx1),
+ .rx(phy0_rx),
.crs_dv(phy0_crs),
.data(rxdata),
.valid(rxvalid),
.eop(rxeop)
);
+wire go;
+
+reg [7:0]txptr = 0;
+reg [7:0]pdata[0:63];
+initial $readmemh("testpacket.hex", pdata);
+
+wire txbusy;
+wire txadvance;
+wire [7:0]txdata = pdata[txptr[5:0]];
+reg txpacket = 0;
+
+always @(posedge clk50) begin
+ if (txpacket) begin
+ if (txadvance) begin
+ txptr <= txptr + 1;
+ if (txptr == 63) begin
+ txpacket <= 0;
+ txptr <= 0;
+ end
+ end
+ end else if (go) begin
+ txpacket <= 1;
+ end
+end
+
+eth_rmii_tx phy0tx(
+ .clk50(clk50),
+ .tx(phy0_tx),
+ .txen(phy0_txen),
+ .data(txdata),
+ .packet(txpacket),
+ .busy(txbusy),
+ .advance(txadvance)
+ );
+
(* keep_hierarchy = "yes" *)
packetlogger log0(
.clk50(clk50),
.rxdata(rxdata),
.rxvalid(rxvalid),
- .rxeop(rxeop)
+ .rxeop(rxeop),
+ .go(go)
);
endmodule
@@ -81,7 +112,8 @@ module packetlogger(
input clk50,
input [7:0]rxdata,
input rxvalid,
- input rxeop
+ input rxeop,
+ output reg go = 0
);
reg [11:0]rdptr = 0;
@@ -113,7 +145,8 @@ always_comb begin
next_rdptr = rdptr;
bufrd = 0;
if (rxvalid | rxeop) begin
- next_rxptr = rxptr + 1;
+ if (rxptr != 12'hFFF)
+ next_rxptr = rxptr + 1;
end
if (dbg_rd) begin
if (dbg_addr == 1) begin
@@ -132,6 +165,11 @@ end
always_ff @(posedge clk50) begin
rxptr <= next_rxptr;
rdptr <= next_rdptr;
+ if (dbg_wr) begin
+ go <= 1;
+ end else begin
+ go <= 0;
+ end
end
(* keep_hierarchy = "yes" *)
diff --git a/hdl/zybo_eth.xdc b/hdl/zybo_eth.xdc
@@ -32,13 +32,13 @@ set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
##Pmod Header JB
##IO_L15N_T2_DQS_34
-set_property PACKAGE_PIN U20 [get_ports {phy0_rx1}]
-set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx1}]
+set_property PACKAGE_PIN U20 [get_ports {phy0_rx[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx[1]}]
##IO_L15P_T2_DQS_34
-set_property PACKAGE_PIN T20 [get_ports {phy0_tx0}]
-set_property IOSTANDARD LVCMOS33 [get_ports {phy0_tx0}]
-set_property SLEW FAST [get_ports {phy0_tx0}]
+set_property PACKAGE_PIN T20 [get_ports {phy0_tx[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_tx[0]}]
+set_property SLEW FAST [get_ports {phy0_tx[0]}]
##IO_L16N_T2_34
set_property PACKAGE_PIN W20 [get_ports {phy0_mdc}]
@@ -49,8 +49,8 @@ set_property PACKAGE_PIN V20 [get_ports {phy0_crs}]
set_property IOSTANDARD LVCMOS33 [get_ports {phy0_crs}]
##IO_L17N_T2_34
-set_property PACKAGE_PIN Y19 [get_ports {phy0_rx0}]
-set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx0}]
+set_property PACKAGE_PIN Y19 [get_ports {phy0_rx[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx[0]}]
##IO_L17P_T2_34
set_property PACKAGE_PIN Y18 [get_ports {phy0_txen}]
@@ -58,9 +58,9 @@ set_property IOSTANDARD LVCMOS33 [get_ports {phy0_txen}]
set_property SLEW FAST [get_ports {phy0_txen}]
##IO_L22N_T3_34
-set_property PACKAGE_PIN W19 [get_ports {phy0_mdio}]
-set_property IOSTANDARD LVCMOS33 [get_ports {phy0_mdio}]
-set_property SLEW FAST [get_ports {phy0_mdio}]
+set_property PACKAGE_PIN W19 [get_ports {phy0_tx[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_tx[1]}]
+set_property SLEW FAST [get_ports {phy0_tx[1]}]
##IO_L22P_T3_34
set_property PACKAGE_PIN W18 [get_ports {phy0_clk}]
