commit 7963051ca5b4c23bc8397e70e66f121a5a2529c8
parent 48c978e056122f8ee522d2e51244994b31f34543
Author: Travis Geiselbrecht <geist@foobox.com>
Date: Tue, 2 Sep 2014 19:15:36 -0700
zybo-adc: add new adc test bed project
Instantiates a XADC and adds a register based interface to continually
sample 8 of the channels.
Diffstat:
| M | Makefile | | | 8 | ++++++++ |
| A | hdl/zybo_adc.sv | | | 211 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | hdl/zybo_adc.xdc | | | 123 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
3 files changed, 342 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
@@ -8,6 +8,14 @@ MODULE_SRCS := hdl/eth_mdio.sv
MODULE_SRCS += hdl/test/eth_mdio_test.sv
include build/verilator-sim.mk
+MODULE_NAME := zybo-adc
+MODULE_PART := xc7z010clg400-1
+MODULE_SRCS := hdl/zybo_adc.sv
+MODULE_SRCS += hdl/axi_ifc.sv hdl/axi_registers.sv
+MODULE_SRCS += hdl/zynq_ps_1m.sv
+MODULE_SRCS += hdl/zybo_adc.xdc
+include build/vivado-bitfile.mk
+
MODULE_NAME := zybo-simple-io
MODULE_PART := xc7z010clg400-1
MODULE_SRCS := hdl/zybo_simple_io.sv
diff --git a/hdl/zybo_adc.sv b/hdl/zybo_adc.sv
@@ -0,0 +1,211 @@
+// Copyright 2014 Brian Swetland <swetland@frotz.net>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`timescale 1ns / 1ps
+
+module top(
+ input clk,
+ input [3:0]sw,
+ input [3:0]btn,
+ input [3:0]ja_p,
+ input [3:0]ja_n,
+ output [3:0]jb_p,
+ output [3:0]jb_n,
+ output reg [3:0]led
+ );
+
+axi_ifc #(.IWIDTH(12),.AXI3(1)) axi_ctl();
+
+wire fclk;
+wire axiclk = clk; // 125Mhz clock from external ethernet phy
+
+zynq_ps7 zynq(
+ .fclk0(fclk),
+ .m_axi_gp0_clk(axiclk),
+ .m_axi_gp0(axi_ctl)
+ );
+
+wire [15:0] aux_channel_n;
+wire [15:0] aux_channel_p;
+
+assign aux_channel_n[14] = ja_n[0];
+assign aux_channel_p[14] = ja_p[0];
+assign aux_channel_n[7] = ja_n[1];
+assign aux_channel_p[7] = ja_p[1];
+assign aux_channel_n[15] = ja_n[2];
+assign aux_channel_p[15] = ja_p[2];
+assign aux_channel_n[6] = ja_n[3];
+assign aux_channel_p[6] = ja_p[3];
+
+reg adc_den;
+reg adc_dwe;
+reg [15:0] adc_din;
+wire [15:0] adc_dout;
+reg [6:0] adc_daddr;
+wire adc_drdy;
+
+wire [4:0] adc_channel;
+wire adc_eoc;
+wire adc_eos;
+wire adc_busy;
+
+(* DONT_TOUCH = "true" *)
+XADC #(
+ .INIT_40(16'h9000),// averaging of 16 selected for external channels
+ .INIT_41(16'h2ef0),// Continuous Seq Mode, Disable unused ALMs, Enable calibration
+ .INIT_42(16'h0500),// DCLK divide 125Mhz / 5
+ .INIT_48(16'b0000011100000001),// CHSEL1 - enable Temp, VCCINT, VCCAUX, and calibration
+ .INIT_49(16'b1100000011000000),// CHSEL2 - enable aux channels 15, 14, 7, 6
+)
+adc0(
+ .DI(adc_din), // 16 bit in
+ .DO(adc_dout), // 16 bit out
+ .DADDR(adc_daddr), // 7 bit address
+ .DEN(adc_den), // enable
+ .DWE(adc_dwe), // write enable
+ .DCLK(axiclk), // clock
+ .DRDY(adc_drdy), // data ready out
+ .RESET(0), // reset
+ .CONVST(0), // not used
+ .CONVSTCLK(0), // not used
+
+ .VP(0),
+ .VN(0),
+ .VAUXN(aux_channel_n[15:0]),
+ .VAUXP(aux_channel_p[15:0]),
+
+ .ALM(), // alarm outputs
+ .OT(), // over temp alarm output
+
+ .MUXADDR(),// not used
+ .CHANNEL(adc_channel), // channel output
+
+ .EOC(adc_eoc), // end of conversion
+ .EOS(adc_eos), // end of sequence
+ .BUSY(adc_busy), // busy during adc conversion
+
+ .JTAGBUSY(),// not used
+ .JTAGLOCKED(),// not used
+ .JTAGMODIFIED()// not used
+);
+
+parameter integer ADC_REG_COUNT = 8;
+reg [15:0] adc_data [ADC_REG_COUNT];
+
+typedef enum {
+ WAIT_FOR_EOS,
+ READ_REG,
+ READ_REG_WAIT
+} state_t;
+
+state_t state = WAIT_FOR_EOS;
+int reg_count;
+reg [6:0] reg_num;
+
+/* mapping of current register count to XADC register */
+always_comb begin
+ case (reg_count)
+ 0: reg_num = 7'h0; // temperature
+ 1: reg_num = 7'h1; // VCCINT
+ 2: reg_num = 7'h2; // VCCAUX
+ 3: reg_num = 7'h5; // VCCREFN
+ 4: reg_num = 7'h10 + 7'd14; // AD14
+ 5: reg_num = 7'h10 + 7'd6; // AD6
+ 6: reg_num = 7'h10 + 7'd15; // AD15
+ 7: reg_num = 7'h10 + 7'd7; // AD7
+ default: reg_num = 0;
+ endcase
+end
+
+/* wait for EOS then pull out readings from each ADC we care about */
+always_ff @(posedge axiclk) begin
+ adc_den = 0;
+ adc_dwe = 0;
+ adc_daddr = 0;
+ adc_din = 0;
+ case (state)
+ WAIT_FOR_EOS: begin
+ reg_count = 0;
+ if (adc_eos == 1) state = READ_REG;
+ end
+ READ_REG: begin
+ if (adc_drdy == 0) begin
+ adc_den = 1;
+ adc_daddr = reg_num[6:0];
+ state = READ_REG_WAIT;
+ end
+ end
+ READ_REG_WAIT: begin
+ if (adc_drdy) begin
+ adc_data[reg_count] <= adc_dout;
+ reg_count = reg_count + 1;
+ if (reg_count == ADC_REG_COUNT) begin
+ state = WAIT_FOR_EOS;
+ end else begin
+ state = READ_REG;
+ end
+ end
+ end
+ endcase
+end
+
+/* AXI stuffs */
+wire [31:0]wdata;
+reg [31:0]rdata;
+wire [2:0]wreg;
+wire [2:0]rreg;
+wire wr;
+wire rd;
+
+axi_registers #(
+ .R_ADDR_WIDTH(3)
+)
+regs(
+ .clk(axiclk),
+ .s(axi_ctl),
+ .o_rreg(rreg),
+ .o_wreg(wreg),
+ .i_rdata(rdata),
+ .o_wdata(wdata),
+ .o_rd(rd),
+ .o_wr(wr)
+ );
+
+always_comb begin
+ rdata = { 16'h0, adc_data[rreg[2:0]] };
+end
+
+always_ff @(posedge axiclk) begin
+ if (wr) begin
+ case (wreg)
+ 0: ;
+ 1: ;
+ 2: ;
+ 3: ;
+ endcase
+ end
+end
+
+// debugging
+assign led[0] = adc_eoc;
+assign led[1] = adc_eos;
+assign led[2] = adc_busy;
+
+assign jb_p[0] = adc_eoc;
+assign jb_p[1] = adc_eos;
+assign jb_p[2] = adc_busy;
+
+endmodule
+
+// vim: set noexpandtab:
diff --git a/hdl/zybo_adc.xdc b/hdl/zybo_adc.xdc
@@ -0,0 +1,123 @@
+##Clock signal
+##IO_L11P_T1_SRCC_35
+set_property PACKAGE_PIN L16 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]
+
+##Switches
+##IO_L19N_T3_VREF_35
+set_property PACKAGE_PIN G15 [get_ports {sw[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+
+##IO_L24P_T3_34
+set_property PACKAGE_PIN P15 [get_ports {sw[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+
+##IO_L4N_T0_34
+set_property PACKAGE_PIN W13 [get_ports {sw[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+
+##IO_L9P_T1_DQS_34
+set_property PACKAGE_PIN T16 [get_ports {sw[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
+
+##Buttons
+##IO_L20N_T3_34
+set_property PACKAGE_PIN R18 [get_ports {btn[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {btn[0]}]
+
+##IO_L24N_T3_34
+set_property PACKAGE_PIN P16 [get_ports {btn[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {btn[1]}]
+
+##IO_L18P_T2_34
+set_property PACKAGE_PIN V16 [get_ports {btn[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {btn[2]}]
+
+##IO_L7P_T1_34
+set_property PACKAGE_PIN Y16 [get_ports {btn[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]
+
+##LEDs
+##IO_L23P_T3_35
+set_property PACKAGE_PIN M14 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+
+##IO_L23N_T3_35
+set_property PACKAGE_PIN M15 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+
+##IO_0_35
+set_property PACKAGE_PIN G14 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+
+##IO_L3N_T0_DQS_AD1N_35
+set_property PACKAGE_PIN D18 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+
+#Pmod Header JA (XADC)
+#IO_L21N_T3_DQS_AD14N_35
+set_property PACKAGE_PIN N16 [get_ports {ja_n[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ja_n[0]}]
+
+##IO_L21P_T3_DQS_AD14P_35
+set_property PACKAGE_PIN N15 [get_ports {ja_p[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ja_p[0]}]
+
+#IO_L22N_T3_AD7N_35
+set_property PACKAGE_PIN L15 [get_ports {ja_n[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ja_n[1]}]
+
+#IO_L22P_T3_AD7P_35
+set_property PACKAGE_PIN L14 [get_ports {ja_p[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ja_p[1]}]
+
+#IO_L24N_T3_AD15N_35
+set_property PACKAGE_PIN J16 [get_ports {ja_n[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ja_n[2]}]
+
+#IO_L24P_T3_AD15P_35
+set_property PACKAGE_PIN K16 [get_ports {ja_p[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ja_p[2]}]
+
+#IO_L20N_T3_AD6N_35
+set_property PACKAGE_PIN J14 [get_ports {ja_n[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ja_n[3]}]
+
+#IO_L20P_T3_AD6P_35
+set_property PACKAGE_PIN K14 [get_ports {ja_p[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ja_p[3]}]
+
+#Pmod Header JB
+#IO_L15N_T2_DQS_34
+set_property PACKAGE_PIN U20 [get_ports {jb_n[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {jb_n[0]}]
+
+#IO_L15P_T2_DQS_34
+set_property PACKAGE_PIN T20 [get_ports {jb_p[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {jb_p[0]}]
+
+#IO_L16N_T2_34
+set_property PACKAGE_PIN W20 [get_ports {jb_n[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {jb_n[1]}]
+
+#IO_L16P_T2_34
+set_property PACKAGE_PIN V20 [get_ports {jb_p[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {jb_p[1]}]
+
+#IO_L17N_T2_34
+set_property PACKAGE_PIN Y19 [get_ports {jb_n[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {jb_n[2]}]
+
+#IO_L17P_T2_34
+set_property PACKAGE_PIN Y18 [get_ports {jb_p[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {jb_p[2]}]
+
+#IO_L22N_T3_34
+set_property PACKAGE_PIN W19 [get_ports {jb_n[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {jb_n[3]}]
+
+#IO_L22P_T3_34
+set_property PACKAGE_PIN W18 [get_ports {jb_p[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {jb_p[3]}]
+
