commit 8b7566e0f70f43af190d2185f3bd69037b27822d
parent 20db1eceb0d6fed70d904296e7d8992e2da424c5
Author: Brian Swetland <swetland@frotz.net>
Date: Sun, 27 Jul 2014 20:51:22 -0700
eth-capture-test basic packet capture testbench
Diffstat:
3 files changed, 187 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
@@ -61,6 +61,21 @@ MODULE_SRCS += hdl/eth_rmii_tx.sv
MODULE_SRCS += hdl/eth_rmii_rx.sv
include build/verilator-sim.mk
+MODULE_NAME := eth-capture-test
+MODULE_SRCS := hdl/test/eth_capture_test.sv
+MODULE_SRCS += hdl/test/eth_packet_gen.sv
+MODULE_SRCS += hdl/eth_capture.sv
+MODULE_SRCS += hdl/eth_rmii_tx.sv
+MODULE_SRCS += hdl/eth_rmii_rx.sv
+MODULE_SRCS += hdl/pkt_bytes_to_words.sv
+MODULE_SRCS += hdl/xilinx_async_fifo.sv
+MODULE_SRCS += hdl/sync_oneway.sv
+MODULE_SRCS += hdl/axi_ifc.sv
+MODULE_SRCS += hdl/axi_dma_writer.sv
+MODULE_SRCS += hdl/axi_sram.sv
+#include build/verilator-sim.mk
+include build/vivado-xsim.mk
+
MODULE_NAME := zybo-eth
MODULE_PART := xc7z010clg400-1
MODULE_SRCS := hdl/zybo_eth.sv
diff --git a/hdl/test/eth_capture_test.sv b/hdl/test/eth_capture_test.sv
@@ -0,0 +1,98 @@
+// Copyright 2014 Brian Swetland <swetland@frotz.net>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`timescale 1ns / 1ps
+
+`ifdef verilator
+module testbench(input clk);
+`else
+module testbench();
+reg clk = 0;
+always #5 clk = ~clk;
+`endif
+
+reg clk50 = 0;
+always @(posedge clk)
+ clk50 = ~clk50;
+
+wire [1:0]eth_dat;
+wire eth_pkt;
+wire done;
+
+reg pkt_gen_start = 0;
+
+eth_packet_gen #(
+ .PACKET_COUNT(5),
+ .PACKET_LENGTH(277)
+ ) pgen0 (
+ .clk50(clk50),
+ .data(eth_dat),
+ .packet(eth_pkt),
+ .start(pkt_gen_start),
+ .done(done)
+ );
+
+wire [7:0]rxdata;
+wire rxvalid;
+wire rxeop;
+wire rxsop;
+
+eth_rmii_rx rx0(
+ .clk50(clk50),
+ .rx(eth_dat),
+ .crs_dv(eth_pkt),
+ .data(rxdata),
+ .valid(rxvalid),
+ .eop(rxeop),
+ .sop(rxsop),
+ .out_tx(),
+ .out_txen()
+ );
+
+axi_ifc #(.AXI3(1)) axi_dma();
+
+reg cap_reset = 0;
+
+eth_capture cap0(
+ .clk50(clk50),
+ .rxsop(rxsop),
+ .rxeop(rxeop),
+ .rxdata(rxdata),
+ .rxvalid(rxvalid),
+ .clk(clk),
+ .reset(cap_reset),
+ .axi_dma(axi_dma)
+ );
+
+axi_sram sram0(
+ .clk(clk),
+ .s(axi_dma)
+ );
+
+`ifdef XX
+always @(posedge clk50)
+ if (done)
+ $finish;
+`endif
+
+reg [31:0]evt_cnt = 0;
+always @(posedge clk) begin
+ evt_cnt <= evt_cnt + 1;
+ if (evt_cnt == 150) cap_reset <= 1;
+ if (evt_cnt == 151) cap_reset <= 0;
+ if (evt_cnt == 200) pkt_gen_start <= 1;
+ if (evt_cnt == 100000) $finish;
+end
+
+endmodule
diff --git a/hdl/test/eth_packet_gen.sv b/hdl/test/eth_packet_gen.sv
@@ -0,0 +1,74 @@
+// Copyright 2014 Brian Swetland <swetland@frotz.net>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`timescale 1ns / 1ps
+
+
+
+module eth_packet_gen(
+ input clk50,
+ output [1:0]data,
+ output packet,
+ input start,
+ output reg done = 0
+ );
+
+parameter PACKET_COUNT = 5;
+parameter PACKET_LENGTH = 145;
+
+reg [8:0]pcount = PACKET_COUNT;
+reg [11:0]plength = PACKET_LENGTH;
+reg [11:0]bcount = 0;
+reg active = 0;
+
+reg txpacket = 0;
+wire txbusy;
+wire txadvance;
+
+eth_rmii_tx tx0(
+ .clk50(clk50),
+ .tx(data),
+ .txen(packet),
+ .data(bcount[7:0]),
+ .packet(txpacket),
+ .busy(txbusy),
+ .advance(txadvance)
+ );
+
+always @(posedge clk50) begin
+ if (start) begin
+ active <= 1;
+ end
+ if (txpacket) begin
+ if (txadvance) begin
+ if (bcount == (PACKET_LENGTH - 1)) begin
+ txpacket <= 0;
+ bcount <= 0;
+ end else begin
+ bcount <= bcount + 1;
+ end
+ end
+ end else begin
+ if (active && ~txbusy) begin
+ if (pcount == 0) begin
+ done <= 1;
+ end else begin
+ pcount <= pcount - 1;
+ txpacket <= 1;
+ end
+ end
+ end
+end
+
+endmodule
