commit baeeb5a8633a9861f2437c1a2e796519c1787118
parent 727e9b42330b630a38a708e3a0d732acae19edbf
Author: Brian Swetland <swetland@frotz.net>
Date: Sun, 20 Jul 2014 04:10:38 -0700
zybo ethernet test project
- capture rx packets to a 4k buffer
- allow buffer dump via jtag
Diffstat:
| M | Makefile | | | 9 | +++++++++ |
| A | hdl/zybo_eth.sv | | | 129 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| A | hdl/zybo_eth.xdc | | | 98 | +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
3 files changed, 236 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
@@ -56,6 +56,15 @@ MODULE_SRCS += hdl/eth_rmii_tx.sv
MODULE_SRCS += hdl/eth_rmii_rx.sv
include build/verilator-sim.mk
+MODULE_NAME := zybo-eth
+MODULE_PART := xc7z010clg400-1
+MODULE_SRCS := hdl/zybo_eth.sv
+MODULE_SRCS += hdl/eth_rmii_rx.sv
+MODULE_SRCS += hdl/mmcm_1in_3out.sv
+MODULE_SRCS += hdl/jtag_debug_port.sv
+MODULE_SRCS += hdl/zybo_eth.xdc
+include build/vivado-bitfile.mk
+
clean::
rm -rf sim synth out
diff --git a/hdl/zybo_eth.sv b/hdl/zybo_eth.sv
@@ -0,0 +1,129 @@
+// Copyright 2014 Brian Swetland <swetland@frotz.net>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`timescale 1ns / 1ps
+
+module top(
+ input clk,
+ output [3:0]led,
+
+ output phy0_clk,
+ output phy0_txen,
+ output phy0_tx0,
+ output phy0_mdc,
+ output phy0_mdio,
+ input phy0_crs,
+ input phy0_rx0,
+ input phy0_rx1
+ );
+
+assign led = 0;
+
+wire clk50;
+
+mmcm_1in_3out #(
+ .CLKIN_PERIOD(8.0),
+ .VCO_MUL(8.000),
+ .VCO_DIV(1),
+ .OUT0_DIV(20.000),
+ .OUT1_DIV(10),
+ .OUT2_DIV(10)
+ ) mmcm0 (
+ .i_clk(clk),
+ .o_clk0(clk50),
+ .o_clk1(),
+ .o_clk2()
+ );
+
+assign phy0_clk = clk50;
+assign phy0_mdc = 1;
+assign phy0_mdio = 0;
+assign phy0_tx0 = 0;
+assign phy0_txen = 0;
+
+wire [7:0]rxdata;
+wire rxvalid;
+wire rxeop;
+
+(* keep_hierarchy = "yes" *)
+eth_rmii_rx phy0(
+ .clk50(clk50),
+ .rx0(phy0_rx0),
+ .rx1(phy0_rx1),
+ .crs_dv(phy0_crs),
+ .data(rxdata),
+ .valid(rxvalid),
+ .eop(rxeop)
+ );
+
+(* keep_hierarchy = "yes" *)
+packetlogger log0(
+ .clk50(clk50),
+ .rxdata(rxdata),
+ .rxvalid(rxvalid),
+ .rxeop(rxeop)
+ );
+
+endmodule
+
+module packetlogger(
+ input clk50,
+ input [7:0]rxdata,
+ input rxvalid,
+ input rxeop
+ );
+
+reg [11:0]rdptr = 0;
+reg [11:0]rxptr = 0;
+reg [8:0]rxbuffer[0:4095];
+
+always_ff @(posedge clk50) begin
+ if (rxvalid | rxeop) begin
+ rxbuffer[rxptr] <= { rxeop, rxdata };
+ if (rxptr != 12'd4095)
+ rxptr <= rxptr + 1;
+ end
+end
+
+wire [31:0]dbg_wdata;
+reg [31:0]dbg_rdata;
+wire [2:0]dbg_addr;
+wire dbg_rd;
+wire dbg_wr;
+
+always_ff @(posedge clk50) begin
+ if (dbg_rd) begin
+ case (dbg_addr)
+ 0: dbg_rdata <= 32'h12345678;
+ 1: begin
+ dbg_rdata <= { 23'd0, rxbuffer[rdptr] };
+ rdptr <= rdptr + 1;
+ end
+ 2: dbg_rdata <= { 20'd0, rxptr };
+ default: dbg_rdata <= 0;
+ endcase
+ end
+end
+
+(* keep_hierarchy = "yes" *)
+jtag_debug_port port0(
+ .clk(clk50),
+ .o_wdata(dbg_wdata),
+ .i_rdata(dbg_rdata),
+ .o_addr(dbg_addr),
+ .o_rd(dbg_rd),
+ .o_wr(dbg_wr)
+ );
+
+endmodule
diff --git a/hdl/zybo_eth.xdc b/hdl/zybo_eth.xdc
@@ -0,0 +1,98 @@
+
+##Clock signal
+##IO_L11P_T1_SRCC_35
+set_property PACKAGE_PIN L16 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]
+
+# 30 MHz JTAG TCK
+create_clock -period 33.333 -name jtag_tck [get_pins port0/bscan/TCK]
+
+# human readable generated clock name
+create_generated_clock -name clk50 [get_pins mmcm0/mmcm_adv_inst/CLKOUT0]
+
+set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks sys_clk_pin] -group jtag_tck
+
+##LEDs
+##IO_L23P_T3_35
+set_property PACKAGE_PIN M14 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+
+##IO_L23N_T3_35
+set_property PACKAGE_PIN M15 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+
+##IO_0_35
+set_property PACKAGE_PIN G14 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+
+##IO_L3N_T0_DQS_AD1N_35
+set_property PACKAGE_PIN D18 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+
+##Pmod Header JB
+##IO_L15N_T2_DQS_34
+set_property PACKAGE_PIN U20 [get_ports {phy0_rx1}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx1}]
+
+##IO_L15P_T2_DQS_34
+set_property PACKAGE_PIN T20 [get_ports {phy0_tx0}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_tx0}]
+
+##IO_L16N_T2_34
+set_property PACKAGE_PIN W20 [get_ports {phy0_mdc}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_mdc}]
+
+##IO_L16P_T2_34
+set_property PACKAGE_PIN V20 [get_ports {phy0_crs}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_crs}]
+
+##IO_L17N_T2_34
+set_property PACKAGE_PIN Y19 [get_ports {phy0_rx0}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_rx0}]
+
+##IO_L17P_T2_34
+set_property PACKAGE_PIN Y18 [get_ports {phy0_txen}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_txen}]
+
+##IO_L22N_T3_34
+set_property PACKAGE_PIN W19 [get_ports {phy0_mdio}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_mdio}]
+
+##IO_L22P_T3_34
+set_property PACKAGE_PIN W18 [get_ports {phy0_clk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {phy0_clk}]
+
+##Pmod Header JD
+##IO_L5N_T0_34
+#set_property PACKAGE_PIN T15 [get_ports {phy1_rx1}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {phy1_rx1}]
+
+##IO_L5P_T0_34
+#set_property PACKAGE_PIN T14 [get_ports {phy1_tx0}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {phy1_tx0}]
+
+##IO_L6N_T0_VREF_34
+#set_property PACKAGE_PIN R14 [get_ports {phy1_mdc}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {phy1_mdc}]
+
+##IO_L6P_T0_34
+#set_property PACKAGE_PIN P14 [get_ports {phy1_crs}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {phy1_crs}]
+
+##IO_L11N_T1_SRCC_34
+#set_property PACKAGE_PIN U15 [get_ports {phy1_rx0}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {phy1_rx0}]
+
+##IO_L11P_T1_SRCC_34
+#set_property PACKAGE_PIN U14 [get_ports {phy1_txen}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {phy1_txen}]
+
+##IO_L21N_T3_DQS_34
+#set_property PACKAGE_PIN V18 [get_ports {phy1_mdio}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {phy1_mdio}]
+
+##IO_L21P_T3_DQS_34
+#set_property PACKAGE_PIN V17 [get_ports {phy1_clk}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {phy1_clk}]
+
