commit 60be1f2379a1481ab18b56e8be5e802bd052bb18
parent a8c9ea29a446ff7400552b775219ac7f524fb97c
Author: Brian Swetland <swetland@frotz.net>
Date: Tue, 8 Jul 2014 18:08:22 -0700
zybo-simple-io: super-simple test project wiring up LEDs/buttons/switches to AXI
Diffstat:
3 files changed, 140 insertions(+), 0 deletions(-)
diff --git a/Makefile b/Makefile
@@ -3,6 +3,14 @@ include build/init.mk
all:
+MODULE_NAME := zybo-simple-io
+MODULE_PART := xc7z010clg400-1
+MODULE_SRCS := hdl/zybo_simple_io.sv
+MODULE_SRCS += hdl/axi_ifc.sv hdl/axi_registers.sv
+MODULE_SRCS += hdl/zynq_ps_1m.sv
+MODULE_SRCS += hdl/zybo_simple_io.xdc
+include build/vivado-bitfile.mk
+
HDMI_SRCS := \
hdl/hdmi_core.sv \
hdl/mmcm_1in_3out.sv \
diff --git a/hdl/zybo_simple_io.sv b/hdl/zybo_simple_io.sv
@@ -0,0 +1,75 @@
+// Copyright 2014 Brian Swetland <swetland@frotz.net>
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`timescale 1ns / 1ps
+
+module top(
+ input clk,
+ input [3:0]sw,
+ input [3:0]btn,
+ output reg [3:0]led = 0
+ );
+
+axi_ifc #(.IWIDTH(12),.AXI3(1)) axi_ctl();
+
+wire fclk;
+wire axiclk = clk;
+
+zynq_ps7 zynq(
+ .fclk0(fclk),
+ .m_axi_gp0_clk(axiclk),
+ .m_axi_gp0(axi_ctl)
+ );
+
+reg [31:0]dbg_reg = 32'haabbccdd;
+
+wire [31:0]wdata;
+reg [31:0]rdata;
+wire [1:0]wreg;
+wire [1:0]rreg;
+wire wr;
+wire rd;
+
+axi_registers regs(
+ .clk(axiclk),
+ .s(axi_ctl),
+ .o_rreg(rreg),
+ .o_wreg(wreg),
+ .i_rdata(rdata),
+ .o_wdata(wdata),
+ .o_rd(rd),
+ .o_wr(wr)
+ );
+
+always_comb begin
+ case (rreg)
+ 0: rdata = { 28'b0, sw };
+ 1: rdata = { 28'b0, btn };
+ 2: rdata = dbg_reg;
+ 3: rdata = 32'h12345678;
+ endcase
+end
+
+always_ff @(posedge axiclk) begin
+ if (wr) begin
+ case (wreg)
+ 0: led <= wdata[3:0];
+ 1: ;
+ 2: dbg_reg <= wdata;
+ 3: ;
+ endcase
+ end
+end
+
+endmodule
diff --git a/hdl/zybo_simple_io.xdc b/hdl/zybo_simple_io.xdc
@@ -0,0 +1,57 @@
+##Clock signal
+##IO_L11P_T1_SRCC_35
+set_property PACKAGE_PIN L16 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]
+
+##Switches
+##IO_L19N_T3_VREF_35
+set_property PACKAGE_PIN G15 [get_ports {sw[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+
+##IO_L24P_T3_34
+set_property PACKAGE_PIN P15 [get_ports {sw[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+
+##IO_L4N_T0_34
+set_property PACKAGE_PIN W13 [get_ports {sw[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+
+##IO_L9P_T1_DQS_34
+set_property PACKAGE_PIN T16 [get_ports {sw[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
+
+##Buttons
+##IO_L20N_T3_34
+set_property PACKAGE_PIN R18 [get_ports {btn[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {btn[0]}]
+
+##IO_L24N_T3_34
+set_property PACKAGE_PIN P16 [get_ports {btn[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {btn[1]}]
+
+##IO_L18P_T2_34
+set_property PACKAGE_PIN V16 [get_ports {btn[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {btn[2]}]
+
+##IO_L7P_T1_34
+set_property PACKAGE_PIN Y16 [get_ports {btn[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}]
+
+##LEDs
+##IO_L23P_T3_35
+set_property PACKAGE_PIN M14 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+
+##IO_L23N_T3_35
+set_property PACKAGE_PIN M15 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+
+##IO_0_35
+set_property PACKAGE_PIN G14 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+
+##IO_L3N_T0_DQS_AD1N_35
+set_property PACKAGE_PIN D18 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+
