zynq-sandbox

commit 7f1c2faabebc2c5ea090459568d3eb9ef7a4d7f7
parent c31e3b4430160f19fd833f5e71ff9e1c178d3b50
Author: Brian Swetland <swetland@frotz.net>
Date:   Thu, 17 Jul 2014 17:49:33 -0700

list all available targets by default

Diffstat:
M
Makefile
 | 
6
+++++-
M
build/init.mk
 | 
3
+--
M
build/verilator-sim.mk
 | 
3
+++
M
build/vivado-bitfile.mk
 | 
6
++++++

4 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
@@ -1,7 +1,7 @@
 
 include build/init.mk
 
-all:
+all: list-all-targets
 
 MODULE_NAME := zybo-simple-io
 MODULE_PART := xc7z010clg400-1
@@ -47,3 +47,7 @@ include build/verilator-sim.mk
 
 clean::
 	rm -rf sim synth out
+
+list-all-targets::
+	@echo buildable targets:
+	@for x in $(ALL_TARGETS) ; do echo $$x ; done
diff --git a/build/init.mk b/build/init.mk
@@ -19,6 +19,5 @@ VIVADO_FILTER := | grep -e "^INFO:.*Inferred" -e "^WARNING:" -e "^ERROR:"
 VIVADO_FILTER += | grep -v '\[Board 49-26\]'
 endif
 
-IP_ALL :=
-VERILATOR_ALL :=
+ALL_TARGETS :=
 
diff --git a/build/verilator-sim.mk b/build/verilator-sim.mk
@@ -44,5 +44,8 @@ $(MODULE_RUN): _DIR := $(MODULE_OBJDIR)
 $(MODULE_RUN): $(MODULE_BIN)
 	@(cd $(_DIR) && ./Vtestbench)
 
+ALL_TARGETS += $(MODULE_RUN)
+TARGET_$(MODULE_RUN)_DESC := "run verilator simulation"
+
 MODULE_NAME :=
 MODULE_SRCS :=
diff --git a/build/vivado-bitfile.mk b/build/vivado-bitfile.mk
@@ -54,6 +54,12 @@ $(MODULE_NAME)-review: _DIR := $(MODULE_OBJDIR)
 $(MODULE_NAME)-review: $(MODULE_BIT)
 	@(cd $(_DIR) && $(VIVADO) -nolog -nojournal post-route-checkpoint.dcp)
 
+
+ALL_TARGETS += $(MODULE_NAME)
+ALL_TARGETS += $(MODULE_NAME)-review
+TARGET_$(MODULE_NAME)_DESC := "build xilinx bitfile"
+TARGET_$(MODULE_NAME)-review_DESC := "build bitfile and review in vivado"
+
 MODULE_NAME :=
 MODULE_SRCS :=
 MODULE_PART :=