cpu32

commit edf7e36c21f51909b404cf90d41cab5cc6b34d42
parent f6f9132373295fa8b9dd5a53d3f2acb1464374da
Author: Brian Swetland <swetland@frotz.net>
Date:   Sun,  5 Feb 2012 05:53:05 -0800

declutter the top of the repository

Diffstat:
M
Makefile
 | 
9
++++++---
R
rom.asm -> rom.s
 | 
0

R
alu.v -> verilog/alu.v
 | 
0

R
cpu32.v -> verilog/cpu32.v
 | 
0

R
library.v -> verilog/library.v
 | 
0

R
ram.v -> verilog/ram.v
 | 
0

R
regfile.v -> verilog/regfile.v
 | 
0

R
rom.v -> verilog/rom.v
 | 
0

R
testbench.v -> verilog/testbench.v
 | 
0

9 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
@@ -1,14 +1,17 @@
 # Copyright 2012, Brian Swetland.  Use at your own risk.
 
-SRC := testbench.v cpu32.v alu.v ram.v rom.v regfile.v library.v
+SRC := verilog/testbench.v
+SRC += verilog/ram.v verilog/rom.v
+SRC += verilog/cpu32.v verilog/alu.v verilog/regfile.v
+SRC += verilog/library.v
 
 all: a32 testbench
 
 testbench: $(SRC) rom.txt
 	iverilog -o testbench $(SRC)
 
-rom.txt: rom.asm
-	./a32 rom.asm rom.txt
+rom.txt: rom.s
+	./a32 rom.s rom.txt
 
 a32: a32.c
 	gcc -g -Wall -o a32 a32.c
diff --git a/rom.asm b/rom.s
diff --git a/alu.v b/verilog/alu.v
diff --git a/cpu32.v b/verilog/cpu32.v
diff --git a/library.v b/verilog/library.v
diff --git a/ram.v b/verilog/ram.v
diff --git a/regfile.v b/verilog/regfile.v
diff --git a/rom.v b/verilog/rom.v
diff --git a/testbench.v b/verilog/testbench.v