commit 46e23bbc9a404b70cea02c6bc093408ac5e00c43
parent 37c5c9410964561e027fbf9959aead870922f05c
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 15 Dec 2018 08:17:50 -0800
cleanup: add `default_nettype none to all verilog sources
Diffstat:
21 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/hdl/board_icebreaker_hdmi111.v b/hdl/board_icebreaker_hdmi111.v
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
module top(
input clk12m_in,
output hdmi_red,
diff --git a/hdl/board_icebreaker_vga444.v b/hdl/board_icebreaker_vga444.v
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
module top(
input clk12m_in,
output [3:0]vga_red,
diff --git a/hdl/board_lattice_evb.v b/hdl/board_lattice_evb.v
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
module top(
input clk12m_in,
output [1:0]vga_red,
diff --git a/hdl/cpu16.sv b/hdl/cpu16.sv
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
`timescale 1ns / 1ps
module cpu16(
diff --git a/hdl/cpu16_alu.sv b/hdl/cpu16_alu.sv
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
module cpu16_alu(
input reg [3:0]op,
input reg [15:0]x,
diff --git a/hdl/cpu16_regs.sv b/hdl/cpu16_regs.sv
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
module cpu16_regs(
input clk,
input [2:0]asel,
diff --git a/hdl/crc8_serial.sv b/hdl/crc8_serial.sv
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
// 0x9C 10011100x // koopman notation (low bit implied)
// 0x39 x00111001 // truncated notation (high bit implied)
diff --git a/hdl/lattice/pll_12_25.v b/hdl/lattice/pll_12_25.v
@@ -1,3 +1,5 @@
+`default_nettype none
+
module pll_12_25(
input clk12m_in,
output clk12m_out,
diff --git a/hdl/nexys4.sv b/hdl/nexys4.sv
@@ -1,6 +1,8 @@
// Copyright 2015, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
module top(
input clk,
output reg[15:0]led
diff --git a/hdl/scope.sv b/hdl/scope.sv
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
// Captures up to 16K samples of 64 bits while trace_en
// Plays them back over the uart when ~trace_en
diff --git a/hdl/simram.sv b/hdl/simram.sv
@@ -1,6 +1,8 @@
// Copyright 2015, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
`timescale 1ns / 1ps
import "DPI-C" function void dpi_mem_write(int addr, int data);
diff --git a/hdl/spi_debug_ifc.v b/hdl/spi_debug_ifc.v
@@ -1,6 +1,8 @@
// Copyright 2015, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
`timescale 1ns / 1ps
module spi_debug_ifc(
diff --git a/hdl/system_cpu16_vga40x30.v b/hdl/system_cpu16_vga40x30.v
@@ -1,6 +1,8 @@
// Copyright 2015, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
`timescale 1ns / 1ps
`define WITH_CPU
diff --git a/hdl/testbench.sv b/hdl/testbench.sv
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
`timescale 1ns / 1ps
module testbench(
diff --git a/hdl/testvga.sv b/hdl/testvga.sv
@@ -1,6 +1,8 @@
// Copyright 2015, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
`timescale 1ns / 1ps
`define HEX_PATHS
diff --git a/hdl/uart_debug_ifc.sv b/hdl/uart_debug_ifc.sv
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
module uart_debug_ifc(
input sys_clk,
output sys_wr,
diff --git a/hdl/uart_rx.sv b/hdl/uart_rx.sv
@@ -1,6 +1,8 @@
// Copyright 2018, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
// Assumes clk is 12M and baudrate is 1M
// TODO: parameterize this a bit
diff --git a/hdl/vga/chardata.v b/hdl/vga/chardata.v
@@ -9,6 +9,8 @@
//
// vram_addr/vram_data: connect to sync sram
+`default_nettype none
+
`timescale 1ns/1ns
module pixeldata #(
diff --git a/hdl/vga/vga.v b/hdl/vga/vga.v
@@ -1,6 +1,8 @@
// Copyright 2012, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
`timescale 1ns/1ns
// Vert: 2xSync 30xBack 480xData 12xFront -> 524 lines
diff --git a/hdl/vga/vga40x30x2.v b/hdl/vga/vga40x30x2.v
@@ -1,6 +1,8 @@
// Copyright 2012, Brian Swetland <swetland@frotz.net>
// Licensed under the Apache License, Version 2.0.
+`default_nettype none
+
module vga40x30x2 #(
parameter BPP = 2
)(
diff --git a/hdl/vga/videoram.v b/hdl/vga/videoram.v
@@ -3,6 +3,8 @@
//
// sync sram with independent read/write addressing
+`default_nettype none
+
`timescale 1ns/1ns
module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) (
