commit e4ed0a9a6e38b1e79c2f9d7270bd51a8df569783
parent c74f68f48a3f170b187ebc71ee48fdc3175c63c0
Author: Brian Swetland <swetland@frotz.net>
Date: Sat, 25 Jan 2020 15:31:00 -0800
build,test: unified test logging, error/exit process
- update makefile to include "make test" to build and
run all simulations
- more testbench.cpp adjustments
- prefix test projects with test-
Diffstat:
11 files changed, 90 insertions(+), 66 deletions(-)
diff --git a/Makefile b/Makefile
@@ -12,6 +12,8 @@ help: list-all-targets
all: build-all-buildable
+test: run-all-tests
+
$(foreach p,$(wildcard project/*.def),$(call project,$p))
clean::
@@ -54,6 +56,7 @@ tools:: out/a16 out/d16 out/icetool out/udebug out/crctool
build-all-buildable:: $(ALL_BUILDS) tools
+run-all-tests:: $(patsubst %,%-vsim,$(filter test-%,$(ALL_BUILDS)))
#### CPU16 TESTS ####
diff --git a/build/verilator-sim.mk b/build/verilator-sim.mk
@@ -33,8 +33,9 @@ $(PROJECT_BIN): $(PROJECT_SRCS) $(PROJECT_DEF) src/testbench.cpp
$(PROJECT_NAME): $(PROJECT_BIN)
+$(PROJECT_RUN): _LOGFILE := $(PROJECT_OBJDIR)/simulation.log
$(PROJECT_RUN): $(PROJECT_BIN)
- @$<
+ @$< > $(_LOGFILE)
ALL_TARGETS += $(PROJECT_NAME) $(PROJECT_RUN)
ALL_BUILDS += $(PROJECT_NAME)
diff --git a/hdl/display/testbench.sv b/hdl/display/testbench.sv
@@ -14,7 +14,9 @@ module testbench(
output [3:0]vga_blu,
output vga_hsync,
output vga_vsync,
- output vga_frame
+ output vga_frame,
+ output reg error = 0,
+ output reg done = 0
);
display #(
diff --git a/hdl/ethernet/eth_crc32_test.sv b/hdl/ethernet/eth_crc32_test.sv
@@ -4,7 +4,9 @@
`default_nettype none
module testbench(
- input clk
+ input clk,
+ output reg error = 0,
+ output reg done = 0
);
reg [8:0]packet[0:103];
@@ -34,16 +36,18 @@ always_ff @(posedge clk) begin
if (~pktdone)
{ pktdone, pktdata } <= packet[pktcount];
pktcount <= pktcount + 7'd1;
- $display("WR=", wr, " DONE=", pktdone, " IDX=", pktcount, " DATA=", pktdata, " CRC=", crc0);
+ $display("WR=", wr, " DONE=", pktdone, " IDX=", pktcount, " DATA=", pktdata, " CRC=", crc0, " NOT=", ~crc0);
if (pktdone) begin
if(crc0 == 32'hdebb20e3) begin
$display("SUCCESS");
+ done <= 1;
end else begin
$display("FAILURE");
+ error <= 1;
end
- $finish();
+ done <= 1;
end
- if (pktcount == 105) $finish();
+ if (pktcount == 105) error <= 1;
end
`else
reg [3:0]tick = 4'b0001;
@@ -76,18 +80,20 @@ always_ff @(posedge clk) begin
end
tick <= { tick[0], tick[3:1] };
end
- $display("WR=", wr, " DONE=", pktdone, " IDX=", pktcount, " DATA=", pktdata, " CRCx2=", crc0, " CRCx8=", crc1);
+ $display("WR=", wr, " DONE=", pktdone, " IDX=", pktcount, " DATA=", pktdata, " CRCx2=", crc0, " CRCx8=", crc1, " NOT=", ~crc1);
if (pktdone) begin
if (crc0 != 32'hdebb20e3) begin
$display("CRC32x2 FAILED");
+ error <= 1;
end else if (crc1 != 32'hdebb20e3) begin
$display("CRC32x8 FAILED");
+ error <= 1;
end else begin
$display("SUCCESS");
+ done <= 1;
end
- $finish();
end
- if (pktcount == 105) $finish();
+ if (pktcount == 105) error <= 1;
end
`endif
diff --git a/hdl/testvga.sv b/hdl/testvga.sv
@@ -1,43 +0,0 @@
-// Copyright 2015, Brian Swetland <swetland@frotz.net>
-// Licensed under the Apache License, Version 2.0.
-
-`default_nettype none
-
-`timescale 1ns / 1ps
-
-`define HEX_PATHS
-
-module testbench(
- input clk,
- output [3:0]vga_red,
- output [3:0]vga_grn,
- output [3:0]vga_blu,
- output vga_hsync,
- output vga_vsync,
- output vga_frame
- );
-
-wire [1:0]red;
-wire [1:0]grn;
-wire [1:0]blu;
-
-vga40x30x2 vga(
- .clk25m(clk),
- .red(red),
- .grn(grn),
- .blu(blu),
- .hs(vga_hsync),
- .vs(vga_vsync),
- .fr(vga_frame),
- .active(),
- .vram_waddr(11'b0),
- .vram_wdata(16'b0),
- .vram_we(1'b0),
- .vram_clk(clk)
- );
-
-assign vga_red = { red, red[0], red[0] };
-assign vga_grn = { grn, grn[0], grn[0] };
-assign vga_blu = { blu, blu[0], blu[0] };
-
-endmodule
diff --git a/hdl/vga/testvga.sv b/hdl/vga/testvga.sv
@@ -0,0 +1,45 @@
+// Copyright 2015, Brian Swetland <swetland@frotz.net>
+// Licensed under the Apache License, Version 2.0.
+
+`default_nettype none
+
+`timescale 1ns / 1ps
+
+`define HEX_PATHS
+
+module testbench(
+ input clk,
+ output [3:0]vga_red,
+ output [3:0]vga_grn,
+ output [3:0]vga_blu,
+ output vga_hsync,
+ output vga_vsync,
+ output vga_frame,
+ output reg error = 0,
+ output reg done = 0
+ );
+
+wire [1:0]red;
+wire [1:0]grn;
+wire [1:0]blu;
+
+vga40x30x2 vga(
+ .clk25m(clk),
+ .red(red),
+ .grn(grn),
+ .blu(blu),
+ .hs(vga_hsync),
+ .vs(vga_vsync),
+ .fr(vga_frame),
+ .active(),
+ .vram_waddr(11'b0),
+ .vram_wdata(16'b0),
+ .vram_we(1'b0),
+ .vram_clk(clk)
+ );
+
+assign vga_red = { red, red[0], red[0] };
+assign vga_grn = { grn, grn[0], grn[0] };
+assign vga_blu = { blu, blu[0], blu[0] };
+
+endmodule
diff --git a/project/display.def b/project/test-display.def
diff --git a/project/eth-crc32-test.def b/project/test-eth-crc32.def
diff --git a/project/test-vga40x30.def b/project/test-vga40x30.def
@@ -0,0 +1,7 @@
+
+PROJECT_TYPE := verilator-sim
+
+PROJECT_SRCS := hdl/vga/testvga.sv
+PROJECT_SRCS += hdl/vga/vga40x30x2.sv hdl/vga/vga.sv hdl/vga/videoram.sv hdl/vga/chardata.sv
+
+PROJECT_VOPTS := -CFLAGS -DVGA
diff --git a/project/vga40x30.def b/project/vga40x30.def
@@ -1,7 +0,0 @@
-
-PROJECT_TYPE := verilator-sim
-
-PROJECT_SRCS := hdl/testvga.sv
-PROJECT_SRCS += hdl/vga/vga40x30x2.sv hdl/vga/vga.sv hdl/vga/videoram.sv hdl/vga/chardata.sv
-
-PROJECT_VOPTS := -CFLAGS -DVGA
diff --git a/src/testbench.cpp b/src/testbench.cpp
@@ -199,7 +199,8 @@ int main(int argc, char **argv) {
Verilated::randReset(2);
Vtestbench *testbench = new Vtestbench;
- testbench->clk = 0;
+ testbench->clk = 1;
+
// first tick, line up with gtk's vert lines
testbench->eval();
@@ -214,7 +215,16 @@ int main(int argc, char **argv) {
#define SAVETRACE() do {} while (0)
#endif
- while (!Verilated::gotFinish()) {
+ while (!(testbench->done | testbench->error)) { //Verilated::gotFinish()) {
+ now += 5;
+ testbench->clk = 0;
+ testbench->eval();
+ SAVETRACE();
+#if 0
+ fprintf(stderr, "SDRAM data=%04x data__out=%04x data__en=%x\n",
+ testbench->sdram_data, testbench->sdram_data__out, testbench->sdram_data_en);
+#endif
+
now += 5;
testbench->clk = 1;
testbench->eval();
@@ -226,11 +236,11 @@ int main(int argc, char **argv) {
break;
}
#endif
- now += 5;
- testbench->clk = 0;
- testbench->eval();
- SAVETRACE();
}
+
+ int status = testbench->error ? -1 : 0;
+ fprintf(stderr, "%s: %s\n", argv[0], testbench->error ? "FAIL" : "PASS");
+
#ifdef TRACE
tfp->close();
#endif
@@ -246,6 +256,6 @@ int main(int argc, char **argv) {
write(fd, memory, sizeof(memory));
close(fd);
}
- return 0;
+ return status;
}
